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M80C186XL20 데이터시트 PDF




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부품번호 M80C186XL20 기능
기능 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSOR
제조업체 Intel
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M80C186XL20 데이터시트, 핀배열, 회로
M80C186XL20 16 12 10
16-BIT HIGH-INTEGRATION EMBEDDED PROCESSOR
Y Low Power Full Static Version of
M80C186
Y Operation Modes
Enhanced Mode
DRAM Refresh Control Unit
Power-Save Mode
Direct Interface to 80C187
Compatible Mode
NMOS 80186 Pin-for-Pin
Replacement for Non-Numerics
Applications
Y Integrated Feature Set
Static Modular CPU
Clock Generator
2 Independent DMA Channels
Programmable Interrupt Controller
3 Programmable 16-Bit Timers
Dynamic RAM Refresh Control Unit
Programmable Memory and
Peripheral Chip Select Logic
Programmable Wait State Generator
Local Bus Controller
Power-Save Mode
System-Level Testing Support (High
Impedance Test Mode)
Y Completely Object Code Compatible
with Existing 8086 8088 Software and
Has 10 Additional Instructions over
8086 8088
Y Speed Versions Available
20 MHz (M80C186XL20)
16 MHz (M80C186XL16)
12 5 MHz (M80C186XL12)
10 MHz (M80C186XL)
Y Direct Addressing Capability to
1 MByte Memory and 64 Kbyte I O
Y Complete System Development
Support
All 8086 and 80C186 Software
Development Tools Can Be Used for
M80C186XL System Development
ASM 86 Assembler PL M-86
Pascal-86 Fortran-86 iC-86 and
System Utilities
In-Circuit-Emulator (ICETM-186)
Y Available in 68-Pin
Ceramic Pin Grid Array (PGA)
Y Military Temperature Range
b55 C to a125 C (TC)
The Intel M80C186XL is a Modular Core re-implementation of the M80C186 microprocessor It offers higher
speed and lower power consumption than the standard M80C186 but maintains 100% clock-for-clock func-
tional compatibility Packaging and pinout are also identical
271276 – 1
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT INTEL CORPORATION 1996
March 1995
Order Number 271276-002




M80C186XL20 pdf, 반도체, 판매, 대치품
M80C186XL
Pins Facing Up
Ceramic Pin Grid Array
Pins Facing Down
NOTE
XXXXXXXXA indicates the Intel FPO number
Figure 2 M80C186XL Pinout Diagrams
271276 – 3
4

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M80C186XL20 전자부품, 판매, 대치품
M80C186XL
Symbol
BHE
PGA
Pin No
64
ALE QS0
61
WR QS1
63
RD QSMD
62
ARDY
55
SRDY
49
Table 1 M80C186XL Pin Description (Continued)
Type
Name and Function
O The BHE (Bus High Enable) signal is analogous to A0 in that it is used
to enable data on to the most significant half of the data bus pins D15 –
D8 BHE will be LOW during T1 when the upper byte is transferred and
will remain LOW through T3 AND TW BHE does not need to be latched
BHE will float during HOLD or RESET
In Enhanced Mode BHE will also be used to signify DRAM refresh
cycles A refresh cycle is indicated by both BHE and A0 being HIGH
BHE and A0 Encodings
BHE
A0
Value Value
Function
0 0 Word Transfer
0 1 Byte Transfer on upper half of data bus (D15 – D8)
1 0 Byte Transfer on lower half of data bus (D7 – D0)
1 1 Refresh
O Address Latch Enable Queue Status 0 is provided by the M80C186XL
to latch the address ALE is active HIGH with addresses guaranteed
valid on the trailing edge
O Write Strobe Queue Status 1 indicates that the data on the bus is to be
written into a memory or an I O device It is active LOW and floats
during bus hold or reset When the M80C186XL is in Queue Status
Mode the ALE QS0 and WR QS1 pins provide information about
processor instruction queue interaction
QS1 QS0
Queue Operation
0 0 No queue operation
0 1 First opcode byte fetched from the queue
1 1 Subsequent byte fetched from the queue
1 0 Empty the queue
O I Read Strobe is an active LOW signal which indicates that the
M80C186XL is performing a memory or I O read cycle It is guaranteed
not to go LOW before the A D bus is floated An internal pull-up
ensures that RD QSMD is HIGH during RESET Following RESET the
pin is sampled to determine whether the M80C186XL is to provide ALE
RD and WR or queue status information To enable Queue Status
Mode RD must be connected to GND RD will float during bus HOLD
I Asynchronous Ready informs the M80C186XL that the addressed
memory space or I O device will complete a data transfer The ARDY
pin accepts a rising edge that is asynchronous to CLKOUT and is active
HIGH The falling edge of ARDY must be synchronized to the
M80C186XL clock Connecting ARDY HIGH will always assert the
ready condition to the CPU If this line is unused it should be tied LOW
to yield control to the SRDY pin
I Synchronous Ready informs the M80C186XL that the addressed
memory space or I O device will complete a data transfer The SRDY
pin accepts an active-HIGH input synchronized to CLKOUT The use of
SRDY allows a relaxed system timing over ARDY This is accomplished
by elimination of the one-half clock cycle required to internally
synchonize the ARDY input signal Connecting SRDY high will always
assert the ready condition to the CPU If this line is unused it should be
tied LOW to yield control to the ARDY pin
7

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M80C186XL20

16-BIT HIGH-INTEGRATION EMBEDDED PROCESSOR

Intel
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