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PDF M80C196KB Data sheet ( Hoja de datos )

Número de pieza M80C196KB
Descripción 16-BIT HIGH PERFORMANCE CHMOS MICROCONTROLLER
Fabricantes Intel 
Logotipo Intel Logotipo



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M80C196KB
16-BIT HIGH PERFORMANCE CHMOS
MICROCONTROLLER
Military
Y 232 Byte Register File
Y Register-to-Register Architecture
Y 28 Interrupt Sources 16 Vectors
Y 2 3 ms 16 x 16 Multiply (12 MHz)
Y 4 0 ms 32 16 Divide (12 MHz)
Y Powerdown and Idle Modes
Y Five 8-Bit I O Ports
Y 16-Bit Watchdog Timer
Y Dynamically Configurable 8-Bit or
16-Bit Buswidth
Y Available in 68-Lead PGA and 68-Lead
Ceramic Quad Flat Pack
Y Full Duplex Serial Port
Y High Speed I O Subsystem
Y 16-Bit Timer
Y 16-Bit Up Down Counter with Capture
Y Pulse-Width-Modulated Output
Y Four 16-Bit Software Timers
Y 10-Bit A D Converter with S H
Y 12 MHz Version M80C196KB
Y Available in Two Product Grades
MIL-STD-883 b55 C to a125 C (TC)
Military Temperature Only (MTO)
b55 C to a125 C (TC)
The M80C196KB 16-bit microcontroller is a high performance member of the MCS -96 microcontroller family
The M80C196KB is pin-for-pin compatible and uses a true superset of the M8096 instructions Intel’s CHMOS
process provides a high performance processor along with low power consumption To further reduce power
requirements the processor can be placed into Idle or Powerdown Mode
Bit byte word and some 32-bit operations are available on the M80C196KB With a 12 MHz oscillator a 16-bit
addition takes 0 66 ms and the instruction times average 0 5 ms to 1 5 ms in typical applications
Four high-speed capture inputs are provided to record times when events occur Six high-speed outputs are
available for pulse or waveform generation The high-speed output can also generate four software timers or
start an A D conversion Events can be based on the timer or up down counter
Also provided on-chip are an A D converter with Sample and Hold serial port watchdog timer and a pulse-
width-modulated output signal
October 1993
Figure 1 M80C196KB Block Diagram
271089 – 1
Order Number 271089-006

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M80C196KB pdf
M80C196KB
PACKAGING
The M80C196KB is available in a ceramic pin grid array shown in Figure 2 and a leaded ceramic quad pack
shown in Figure 3 A comparison of the pinouts for both of these package types is shown in Tables 1a – 1c
Figure 2 Pin Grid Array Pinout
271089 – 2
5

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M80C196KB arduino
M80C196KB
Instruction Summary (Continued)
Mnemonic
Operands
Operation (Note 1)
Flags
Notes
Z N C V VT ST
w wRET
0 PC (SP) SP SP a 2
bbbb b b
J (conditional)
w1 PC PC a 8-bit offset (if taken) b b b b b b 5
JC 1 Jump if C e 1 b b b b b b 5
JNC 1 jump if C e 0
bbbb b b 5
JE 1 jump if Z e 1 b b b b b b 5
JNE 1 Jump if Z e 0
bbbb b b 5
JGE 1 Jump if N e 0
bbbb b b 5
JLT 1 Jump if N e 1
bbbb b b 5
JGT
1 Jump if N e 0 and Z e 0
bbbb b b 5
JLE
1 Jump if N e 1 or Z e 1
bbbb b b 5
JH
1 Jump if C e 1 and Z e 0
bbbb b b 5
JNH
1 Jump if C e 0 or Z e 1
bbbb b b 5
JV 1 Jump if V e 0 b b b b b b 5
JNV 1 Jump if V e 1
bbbb b b 5
JVT
1 Jump if VTe 1 Clear VT
bbbb 0 b 5
JNVT
1 Jump if VT e 0 Clear VT
bbbb 0 b 5
JST 1 Jump if ST e 1 b b b b b b 5
JNST
1 Jump if ST e 0
bbbb b b 5
JBS
3 Jump if Specified Bit e 1
b b b b b b 56
JBC
3 Jump if Specified Bit e 0
b b b b b b 56
DJNZ
DJNZW
1 DwDb1
bbbb b b 5
wIf D i 0 then PC PC a 8-bit offset
DEC DECB
NEG NEGB
1 DwDb1
1 Dw0bD
ub
ub
INC INCB
EXT
1 DwDa1
1 D w D D a 2 w Sign (D)
ub
0 0 bb
2
EXTB
1 D w D D a 1 w Sign (D)
00bb 3
NOT NOTB
w1 D Logical Not (D)
0 0 bb
CLR CLRB
1 Dw0
1 0 0 0 bb
SHL SHLB SHLL
SHR SHRB SHRL
2 C w msb - - - - - lsb w 0
2 0 x msb - - - - - lsb x C
ub
0b
7
7
x xSHRA SHRAB SHRAL 2 msb msb - - - - - lsb C
0b
7
SETC
0 Cw1
bb 1 b b b
CLRC
0 Cw0
bb 0 b b b
11

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