Datasheet.kr   

M80C86-2 데이터시트 PDF




Intel에서 제조한 전자 부품 M80C86-2은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 M80C86-2 자료 제공

부품번호 M80C86-2 기능
기능 16-BIT CHMOS MICROPROCESSOR
제조업체 Intel
로고 Intel 로고


M80C86-2 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.



전체 19 페이지수

미리보기를 사용할 수 없습니다

M80C86-2 데이터시트, 핀배열, 회로
M80C86 M80C86-2
16-BIT CHMOS MICROPROCESSOR
MILITARY
Y Pin-for-Pin and Functionally Compatible
to Industry Standard HMOS M8086
Y Fully Static Design with Frequency
Range from D C to
5 MHz for M80C86
8 MHz for M80C86-2
Y Low Power Operation
Operating ICC e 10 mA MHz
Standby ICCS e 500 mA max
Y Bus-Hold Circuitry Eliminates Pull-Up
Resistors
Y Direct Addressing Capability of
1 MByte of Memory
Y Architecture Designed for Powerful
Assembly Language and Efficient High
Level Languages
Y 24 Operand Addressing Modes
Y Byte Word and Block Operations
Y 8 and 16-Bit Signed and Unsigned
Arithmetic
Binary or Decimal
Multiply and Divide
Y Military Temperature Range
b55 C to a125 C (TC)
The Intel M80C86 is a high performance CHMOS version of the industry standard HMOS M8086 16-bit CPU It
is available in 5 and 8 MHz clock rates The M80C86 offers two modes of operation MINimum for small
systems and MAXimum for larger applications such as multiprocessing It is available in 40-pin DIP package
271058 –1
Figure 1 M80C86 CPU Block Diagram
271058 – 2
Figure 2 M80C86 40-Lead DIP Configuration
November 1989
Order Number 271058-005




M80C86-2 pdf, 반도체, 판매, 대치품
M80C86 M80C86-2
Table 1 Pin Description (Continued)
The following pin function descriptions are for the M80C86 M82C88 system in maximum mode (i e
MN MX eVSS) Only the pin functions which are unique to maximum mode are described all other pin func-
tions are as described above
Symbol
S2 S1 S0
Pin No
26– 28
Type
O
Name and Function
STATUS active during T4 T1 and T2 and is returned to the passive
state (1 1 1) during T3 or during TW when READY is HIGH This
status is used by the M82C88 Bus Controller to generate all memory
and I O access control signals Any change by S2 S1 S0 during T4
is used to indicate the beginning of a bus cycle and the return to the
passive state in T3 or TW is used to indicate the end of a bus cycle
These signals float to 3-state OFF(1) in ‘‘hold acknowledge ’’ These
status lines are encoded as shown
RQ GT0
RQ GT1
30 31
S2 S1 S0
0 (LOW)
0
0
0
0
0
1 (HIGH)
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
Characteristics
Interrupt
Acknowledge
Read I O Port
Write I O Port
Halt
Code Access
Read Memory
Write Memory
Passive
I O REQUEST GRANT pins are used by other local bus masters to
force the processor to release the local bus at the end of the
processor’s current bus cycle Each pin is bidirectional with RQ GT0
having higher priority than RQ GT1 RQ GT has an internal pull-up
resistor so may be left unconnected The request grant sequence is
as follows (see timing diagram)
1 A pulse of 1 CLK wide from another local bus master indicates a
local bus request (‘‘hold’’) to the M80C86 (pulse 1)
2 During a T4 or T1 clock cycle a pulse 1 CLK wide from the
M80C86 to the requesting master (pulse 2) indicates that the
M80C86 has allowed the local bus to float and that it will enter the
‘‘hold acknowledge’’ state at the next CLK The CPU’s bus interface
unit is disconnected logically from the local bus during ‘‘hold
acknowledge ’’
3 A pulse 1 CLK wide from the requesting master indicates to the
M80C86 (pulse 3) that the ‘‘hold’’ request is about to end and that
M80C86 can reclaim the local bus at the next CLK
Each master-master exchange of the local bus is a sequence of 3
pulses There must be one dead CLK cycle after each bus exchange
Pulses are active LOW
If the request is made while the CPU is performing a memory cycle it
will release the local bus during T4 of the cycle when all the following
conditions are met
1 Request occurs on or before T2
2 Current cycle is not the low byte of a word (on an odd address)
3 Current cycle is not the first acknowledge of an interrupt
acknowledge sequence
4 A locked instruction is not currently executing
4

4페이지










M80C86-2 전자부품, 판매, 대치품
M80C86 M80C86-2
INTERNAL ARCHITECTURE
The internal functions of the M80C86 processor are
partitioned logically into two processing units The
first is the Bus Interface Unit (BIU) and the second is
the Execution Unit (EU) as shown in the block dia-
gram of Figure 1
These units can interact directly but for the most
part perform as separate asynchronous operational
processors The bus interface unit provides the func-
tions related to instruction fetching and queuing op-
erand fetch and store and address relocation This
unit also provides the basic bus control The overlap
of instruction pre-fetching provided by this unit
serves to increase processor performance through
improved bus bandwidth utilization Up to 6 bytes of
the instruction stream can be queued while waiting
for decoding and execution
The instruction stream queuing mechanism allows
the BIU to keep the memory utilized very efficiently
Whenever there is space for at least 2 bytes in the
queue the BIU will attempt a word fetch memory
cycle This greatly reduces ‘‘dead time’’ on the
memory bus The queue acts as a First-In-First Out
(FIFO) buffer from which the EU extracts instruction
bytes as required If the queue is empty (following a
branch instruction for example) the first byte into
the queue immediately becomes available to the EU
The execution units receives pre-fetched instruc-
tions from the BIU queue and provides un-relocated
operand addresses to the BIU Memory operands
are passed through the BIU for processing by the
EU which passes results to the BIU for storage See
the Instruction Set description for further register set
and architectural descriptions
NOTE
Additional information on memory organization re-
quirements for supporting minimum and maximum
modes bus operation basic system timing and ex-
ternal interface of the M80C86 is described in the
Microsystems Components Handbook
DEVIATION DESCRIPTION
A 20 – 25 ns glitch occurs on the 80C86 80C88 RD
pin immediately following a read cycle The problem
has been fully characterized with the following re-
sults
1 The read cycle must be 4 clocks followed by 2
passive clocks
2 Cycle following the read cycle must be a data
read write or an I O read write
3 The of bytes in the queue required to cause
the glitch varies by instruction
4 The glitch appears on the falling edge of the first
passive clock
5 The magnitude of the glitch depends on the ca-
pacitive loading of the RD pin
6 The glitch occurs for both Min and Max mode
operations
7 VCC variations from 4 5V through 5 5V have no
effect on the glitch
8 Temperature variations (within allowed tempera-
ture range) also have no effect on the glitch
IMPACT ON SYSTEM DESIGN
Systems which use the RD strobe to clock a state
machine or any other edge triggered device are
most vulnerable and most likely to malfunction
The problem may also impact other Min mode sys-
tems particularly those in which the system address
latches are enabled all the time (such as the exam-
ple minimum mode system illustrated in the 80C86
data sheet) In such designs the RD signal is used
to turn off the output buffers of the memory and pe-
ripheral devices connected to the local bus at the
end of a bus cycle A false pulse on the RD pin in a
TP or a T1 state following a read cycle may not allow
for sufficient recovery time for a previously accessed
device The probability of a failure is higher for low
speed designs using slow memory and peripheral
devices which require high recovery times between
successive accesses The problem will not be seen
if the address latches are disabled at the end of any
bus cycle since all the devices connected to the bus
will then be deselected when the false pulse occurs
Most Max mode systems do not use the RD signal
and are therefore not likely to be affected
7

7페이지


구       성 총 19 페이지수
다운로드[ M80C86-2.PDF 데이터시트 ]

당사 플랫폼은 키워드, 제품 이름 또는 부품 번호를 사용하여 검색할 수 있는

포괄적인 데이터시트를 제공합니다.


구매 문의
일반 IC 문의 : 샘플 및 소량 구매
-----------------------------------------------------------------------

IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한
광범위한 전력 반도체를 판매합니다.

전력 반도체 전문업체

상호 : 아이지 인터내셔날

사이트 방문 :     [ 홈페이지 ]     [ 블로그 1 ]     [ 블로그 2 ]



관련 데이터시트

부품번호상세설명 및 기능제조사
M80C86-2

16-BIT CHMOS MICROPROCESSOR

Intel
Intel

DataSheet.kr       |      2020   |     연락처      |     링크모음      |      검색     |      사이트맵