|
|
|
부품번호 | M82C288-6 기능 |
|
|
기능 | BUS CONTROLLER FOR M80286 PROCESSORS | ||
제조업체 | Intel | ||
로고 | |||
M82C288
BUS CONTROLLER FOR M80286 PROCESSORS
(M82C288-10 M82C288-8 M82C288-6)
Military
Y Provides Commands and Controls for
Local and System Bus
Y Wide Flexibility in System
Configurations
Y Implemented in High Speed CHMOS III
Technology
Y Fully Compatible with the HMOS
M82288
Y Fully Static Device
Y Single a5V Supply
Y Available in 20 Pin Cerdip Package
(See Packaging Spec Order 231369)
The Intel M82C288 Bus Controller is a 20-pin CHMOS III component for use in M80C286 microsystems The
M82C288 is fully compatible with its predecessor the HMOS M82288 The bus controller is fully static and
supports a low power mode The bus controller provides command and control outputs with flexible timing
options Separate command outputs are used for memory and I O devices The data bus is controlled with
separate data enable and direction control signals
Two modes of operation are possible via a strapping option MULTIBUS Compatible bus cycles and high
speed bus cycles
20 Pin Cerdip Package
Figure 1 M82C288 Block Diagram
271077 – 1
271077 – 2
Figure 2 M82C288 Pin
Configuration
November 1991
Order Number 271077-006
M82C288
Symbol
INTA
VCC
GND
Type
O
Table 1 Pin Description (Continued)
Name and Function
INTERRUPT ACKNOWLEDGE tells an interrupting device that its interrupt request
is being acknowledged This command output is active LOW The MB and CMDLY
inputs control when this output becomes active READY controls when it becomes
inactive
System Power a5V Power Supply
System Ground 0V
Table 2 Command and Control Outputs for Each Type of Bus Cycle
Type of
Bus Cycle
M IO
S1
S0
Command
Activated
DT R
State
ALE DEN
Issued
Interrupt Acknowledge
0
0 0 INTA
LOW
YES
I O Read
0 0 1 IORC
LOW
YES
I O Write
0 1 0 IOWC
HIGH
YES
None Idle
0 1 1 None
HIGH
NO
Halt Shutdown
1 0 0 None
HIGH
NO
Memory Read
1 0 1 MRDC
LOW
YES
Memory Write
1 1 0 MWTC
HIGH
YES
None Idle
1 1 1 None
HIGH
NO
MCE
Issued
YES
NO
NO
NO
NO
NO
NO
NO
Operating Modes
Two types of buses are supported by the M82C288
MULTIBUS I and non-MULTIBUS I When the MB
input is strapped HIGH MULTIBUS I timing is used
In MULTIBUS I mode the M82C288 delays com-
mand and data activation to meet IEEE-796 require-
ments on address to command active and write data
to command active setup timing MULTIBUS I mode
requires at least one wait state in the bus cycle since
the command outputs are delayed The non-
MULTIBUS I mode does not delay any outputs and
does not require wait states The MB input affects
the timing of the command and DEN outputs
and INTA) control outputs (ALE DEN DT R) and
control inputs (CEN AEN CENL CMDLY MB and
READY) are identical for all read bus cycles Read
cycles differ only in which command output is acti-
vated The MCE control output is only asserted dur-
ing interrupt acknowledge cycles
Write bus cycles activate different control and com-
mand outputs with different timing than read bus cy-
cles Memory write and I O write are write bus cy-
cles whose timing for command outputs (MWTC and
IOWC) control outputs (ALE DEN DT R) and con-
trol inputs (CEN AEN CENL CMDLY MB and
READY) are identical They differ only in which com-
mand output is activated
Command and Control Outputs
The type of bus cycle performed by the local bus
master is encoded in the M IO S1 and S0 inputs
Different command and control outputs are activat-
ed depending on the type of bus cycle Table 2 indi-
cates the cycle decode done by the M82C288 and
the effect on command DT R ALE DEN and MCE
outputs
Bus cycles come in three forms read write and
halt Read bus cycles include memory read I O
read and interrupt acknowledge The timing of the
associated read command outputs (MRDC IORC
Halt bus cycles are different because no command
or control output is activated All control inputs are
ignored until the next bus cycle is started via S1 and
S0
Static Operation
All M82C288 circuitry is of static design Internal reg-
isters and logic are static and require no refresh as
with dynamic circuit design This eliminates the mini-
mum operating frequency restriction placed on the
HMOS M82288 The CHMOS III M82C288 can oper-
ate from DC to the appropriate upper frequency limit
4
4페이지 M82C288
Figures 6 through 10 show the basic command and
control output timing for read and write bus cycles
Halt bus cycles are not shown since they activate no
outputs The basic idle-read-idle and idle-write-idle
bus cycles are shown The signal label CMD repre-
sents the appropriate command output for the bus
cycle For Figures 6 through 10 the CMDLY input is
connected to GND and CENL to VCC The effects of
CENL and CMDLY are described later in the section
on control inputs
Figures 6 7 and 8 show non-MULTIBUS I cycles
MB is cnonected to GND while CEN is connected to
VCC Figure 6 shows a read cycle with no wait states
while Figure 7 shows a write cycle with one wait
state The READY input is shown to illustrate how
wait states are added
Figure 6 Idle-Read-Idle Bus Cycles with MB e 0
271077 – 6
Figure 7 Idle-Write-Idle Bus Cycles with MB e 0
271077 – 7
7
7페이지 | |||
구 성 | 총 20 페이지수 | ||
다운로드 | [ M82C288-6.PDF 데이터시트 ] |
당사 플랫폼은 키워드, 제품 이름 또는 부품 번호를 사용하여 검색할 수 있는 |
구매 문의 | 일반 IC 문의 : 샘플 및 소량 구매 ----------------------------------------------------------------------- IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한 광범위한 전력 반도체를 판매합니다. 전력 반도체 전문업체 상호 : 아이지 인터내셔날 사이트 방문 : [ 홈페이지 ] [ 블로그 1 ] [ 블로그 2 ] |
부품번호 | 상세설명 및 기능 | 제조사 |
M82C288-10 | BUS CONTROLLER FOR M80286 PROCESSORS | Intel |
M82C288-6 | BUS CONTROLLER FOR M80286 PROCESSORS | Intel |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |