Datasheet.kr   

M89141Y-15K6T 데이터시트 PDF




ST Microelectronics에서 제조한 전자 부품 M89141Y-15K6T은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 M89141Y-15K6T 자료 제공

부품번호 M89141Y-15K6T 기능
기능 In-System Programmable ISP Multiple-Memory and Logic FLASHPSD Systems for MCUs
제조업체 ST Microelectronics
로고 ST Microelectronics 로고


M89141Y-15K6T 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.



전체 7 페이지수

미리보기를 사용할 수 없습니다

M89141Y-15K6T 데이터시트, 핀배열, 회로
M89 FAMILY
In-System Programmable (ISP)
Multiple-Memory and Logic FLASH+PSD Systems for MCUs
DATA BRIEFING
s Single Supply Voltage:
– 5 V±10% for M89xxFxY
– 3 V (+20/–10%) for M89xxFxW
s 1 or 2 Mbit of Primary Flash Memory (8 uniform
sectors, 16K x 8, or 32K x 8)
s A second non-volatile memory:
– 256 Kbit (32K x 8) EEPROM (for M8913F1x)
or Flash memory (for M89x3F2x)
– 4 uniform sectors (8K x 8)
s SRAM (16 Kbit, 2K x 8; or 64 Kbit, 8K x 8)
s Over 2,000 Gates of PLD: DPLD and GPLD
s 27 Reconfigurable I/O ports
s Enhanced JTAG Serial Port
s Programmable power management
s Stand-by current:
– 50 µA for M89xxFxY
– 25 µA for M89xxFxW
s High Endurance:
– 100,000 Erase/Write Cycles of Flash Memory
– 10,000 Erase/Write Cycles of EEPROM
– 1,000 Erase/Write Cycles of PLD
PQFP52 (T)
PLCC52 (K)
Figure 1. Logic Diagram
VCC
Table 1. Signal Names
PA0-PA7
Port-A
PB0-PB7
Port-B
PC0-PC7
Port-C
PC2 = Voltage Stand-by
PD0-PD2
Port-D
AD0-AD15
Address/Data
CNTL0-CNTL2
Control
RESET
Reset
VCC Supply Voltage
VSS Ground
8
PA0-PA7
3
CNTL0-
CNTL2
16
AD0-AD15
FLASH+PSD
8
PB0-PB7
8
PC0-PC7
RESET
3
PD0-PD2
VSS
AI02856
June 2000
Complete data available on Data-on-Disc CD-ROM or at www.st.com
1/7




M89141Y-15K6T pdf, 반도체, 판매, 대치품
M89 FAMILY
EPROM or Flash memory, or an external
programmer. To simplify Flash memory updates,
program execution is performed from a secondary
Flash memory (for the M89xxF2x) or EEPROM
(for the M8913F1x) while the primary Flash
memory is being updated. This solution avoids the
complicated hardware and software overhead
necessary to implement IAP.
ST makes available a software development tool,
PSDsoft Express, that generates ANSI-C
compliant code for use with your target MCU. This
code allows you to manipulate the non-volatile
memory (NVM) within the FLASH+PSD. Code
examples are also provided for:
– Flash memory IAP via the UART of the host
MCU
– Memory paging to execute code across several
FLASH+PSD memory pages
FLASH+PSD ARCHITECTURAL OVERVIEW
FLASH+PSD devices contain several major
functional blocks. Figure 3 shows the architecture
of the M89 FLASH+PSD device family. The
functions of each block are described briefly in the
following sections. Many of the blocks perform
multiple functions and are user configurable.
Memory
The 1 or 2 Mbit (128K x 8, or 256K x 8) Flash
memory is the primary memory of the
FLASH+PSD. It is divided into eight equally-sized
sectors that are individually selectable.
The 256 Kbit (32K x 8) secondary EEPROM or
Flash memory is divided into four equally-sized
sectors. Each sector is individually selectable.
The SRAM is intended for use as a scratch-pad
memory or as an extension to the MCU SRAM. If
an external battery is connected to Voltage Stand-
by (VSTBY, PC2), data is retained in the event of
power failure.
Each sector of memory can be located in a
different address space as defined by the user.
The access times for all memory types includes
the address latching and DPLD decoding time.
The M8913F1x has 64 bytes of OTP memory for
product identifiers, serial numbers, calibration
constants, etc..
Page Register
The 8-bit Page Register expands the address
range of the MCU by up to 256 times. The paged
address can be used as part of the address space
to access external memory and peripherals, or
internal memory and I/O. The Page Register can
also be used to change the address mapping of
sectors of the Flash memories into different
memory spaces for IAP.
PLDs
The device contains two PLDs, the Decode PLD
(DPLD) and the General PLD (GPLD), each
optimized for a different function, as shown in
Table 3. The functional partitioning of the PLDs
reduces power consumption, optimizes cost/
performance, and eases design entry.
The Decode PLD (DPLD) is used to decode
addresses and to generate chip selects for the
FLASH+PSD internal memory and registers. The
DPLD has 14 combinatorial outputs, which are
used to select memory sectors and internal
registers. The General PLD (GPLD) can be used
to implement user-defined external chip select
signals and other combinatorial logic functions.
The PLDs consume minimal power. The speed
and power consumption of the PLD is controlled
by the Turbo bit in the PMMR0 register and other
bits in the PMMR2 registers. These registers are
set by the MCU at run-time. There is a slight
penalty to PLD propagation time when invoking
the power management features.
I/O Ports
The FLASH+PSD has 27 individually configurable
I/O pins distributed over the four ports (Port A, B,
C, and D). Each I/O pin can be individually
configured for different functions. Ports can be
configured as standard MCU I/O ports, PLD I/O, or
latched address outputs for MCUs using
multiplexed address/data buses. Ports A and B
can be configured to be open drain.
The JTAG pins can be enabled on Port C for In-
System Programming (ISP).
Port A can also be configured as a data port for a
non-multiplexed bus.
MCU Bus Interface
FLASH+PSD interfaces easily with most 8-bit
MCUs that have either multiplexed or non-
multiplexed address/data buses. The device is
configured to respond to the MCU’s control
signals, which are also used as inputs to the PLDs.
For examples, please see the full data sheet.
JTAG Port
In-System Programming (ISP) can be performed
through the JTAG signals on Port C. This serial
interface allows complete programming of the
entire FLASH+PSD device. A blank device can be
completely programmed for the first time after it is
soldered to the board. The JTAG signals (TMS,
TCK, TSTAT, TERR, TDI, TDO) can be
multiplexed with other functions on Port C. Table 4
indicates the JTAG pin assignments. Four-pin
JTAG is also fully supported.
In-System Programming (ISP)
Using the JTAG signals on Port C, the entire
FLASH+PSD device can be programmed or
4/7

4페이지










M89141Y-15K6T 전자부품, 판매, 대치품
M89 FAMILY
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express writt en approval of STMicroelectronics.
© 2000 STMicroelectronics - All Rights Reserved
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners.
STMicroelectronics GROUP OF COMPANIES
Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain -
Sweden - Switzerland - United Kingdom - U.S.A.
http://www. st.com
7/7

7페이지


구       성 총 7 페이지수
다운로드[ M89141Y-15K6T.PDF 데이터시트 ]

당사 플랫폼은 키워드, 제품 이름 또는 부품 번호를 사용하여 검색할 수 있는

포괄적인 데이터시트를 제공합니다.


구매 문의
일반 IC 문의 : 샘플 및 소량 구매
-----------------------------------------------------------------------

IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한
광범위한 전력 반도체를 판매합니다.

전력 반도체 전문업체

상호 : 아이지 인터내셔날

사이트 방문 :     [ 홈페이지 ]     [ 블로그 1 ]     [ 블로그 2 ]



관련 데이터시트

부품번호상세설명 및 기능제조사
M89141Y-15K6T

In-System Programmable ISP Multiple-Memory and Logic FLASHPSD Systems for MCUs

ST Microelectronics
ST Microelectronics

DataSheet.kr       |      2020   |     연락처      |     링크모음      |      검색     |      사이트맵