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PDF 7C132-25 Data sheet ( Hoja de datos )
| Número de pieza | 7C132-25 | |
| Descripción | 2Kx8 Dual-Port Static RAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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1CY 7C13 2/ CY7C1 36
fax id: 5201
CY7C132/CY7C136
CY7C142/CY7C146
Features
• True Dual-Ported memory cells which allow simulta-
neous reads of the same memory location
• 2K x 8 organization
• 0.65-micron CMOS for optimum speed/power
• High-speed access: 15 ns
• Low operating power: ICC = 90 mA (max.)
• Fully asynchronous operation
• Automatic power-down
• Master CY7C132/CY7C136 easily expands data bus
width to 16 or more bits using slave CY7C142/CY7C146
• BUSY output flag on CY7C132/CY7C136; BUSY input
on CY7C142/CY7C146
• INT flag for port-to-port communication (52-pin
PLCC/PQFP versions)
• Available in 48-pin DIP (CY7C132/142), 52-pin PLCC and
52-pin TQFP (CY7C136/146)
• Pin-compatible and functionally equivalent to
IDT7132/IDT7142
2Kx8 Dual-Port Static RAM
Functional Description
The CY7C132/CY7C136/CY7C142 and CY7C146 are
high-speed CMOS 2K by 8 dual-port static RAMs. Two ports
are provided to permit independent access to any location in
memory. The CY7C132/ CY7C136 can be utilized as either a
standalone 8-bit dual-port static RAM or as a MASTER du-
al-port RAM in conjunction with the CY7C142/CY7C146
SLAVE dual-port device in systems requiring 16-bit or greater
word widths. It is the solution to applications requiring shared
or buffered data such as cache memory for DSP, bit-slice, or
multiprocessor designs.
Each port has independent control pins; chip enable (CE),
write enable (R/W), and output enable (OE). BUSY flags are
provided on each port. In addition, an interrupt flag (INT) is
provided on each port of the 52-pin PLCC version. BUSY sig-
nals that the port is trying to access the same location currently
being accessed by the other port. On the PLCC version, INT
is an interrupt flag indicating that data has been placed in a
unique location (7FF for the left port and 7FE for the right port).
An automatic power-down feature is controlled independently
on each port by the chip enable (CE) pins.
The CY7C132/CY7C142 are available in 48-pin DIP. The
CY7C136/CY7C146 are available in 52-pin PLCC and PQFP.
Logic Block Diagram
Pin Configuration
R/WL
CEL
OEL
I/O7L
I/O0L
BUSYL[1]
A 10L
A 0L
I/O
CONTROL
I/O
CONTROL
ADDRESS
DECODER
MEMORY
ARRAY
ADDRESS
DECODER
INTL[2]
CEL
OEL
R/WL
ARBITRATION
LOGIC
(7C132/7C136 ONLY)
AND
INTERRUPTLOGIC
(7C136/7C146 ONLY)
CER
OER
R/WR
Notes:
1. CY7C132/CY7C136 (Master): BUSY is open drain output and requires pull-up resistor.
CY7C142/CY7C146 (Slave): BUSY is input.
2. Open drain outputs; pull-up resistor required.
R/WR
CER
OER
I/O7R
I/O0R
BUSYR[1]
A 10R
A 0R
INTR[2]
C132-1
DIP
Top View
CEL
R/WL
BUSYL
A10L
OEL
A0L
A1L
A2L
A3L
A4L
A5L
A6L
A7L
A8L
A9L
I/O0L
I/O1L
I/O2L
I/O3L
I/O4L
I/O5L
I/O6L
I/O7L
GND
1 48
2 47
3 46
4 45
5 44
6 43
7 42
8 41
9 40
10 39
11 38
12 7C132 37
13 7C142 36
14 35
15 34
16 33
17 32
18 31
19 30
20 29
21 28
22 27
23 26
24 25
VCC
CER
R/WR
BUSYR
A10R
OER
A0R
A1R
A2R
A3R
A4R
A5R
A6R
A7R
A8R
A9R
I/O7R
I/O6R
I/O5R
I/O4R
I/O3R
I/O2R
I/O1R
I/O0R
C132-2
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
December 1989 – Revised March 27, 1997
1 page  
CY7C132/CY7C136
CY7C142/CY7C146
Switching Characteristics Over the Operating Range[6, 11] (continued)
7C136-15[3,4]
7C146-15
Parameter
Description
Min. Max.
BUSY/INTERRUPT TIMING
tBLA
tBHA
tBLC
tBHC
tPS
tWB
tWH
tBDD
tDDD
BUSY LOW from Address Match
BUSY HIGH from Address Mismatch[16]
15
15
BUSY LOW from CE LOW
BUSY HIGH from CE HIGH[16]
15
15
Port Set Up for Priority
R/W LOW after BUSY LOW[17]
5
0
R/W HIGH after BUSY HIGH
13
BUSY HIGH to Valid Data
15
Write Data Valid to Read Data Valid
Note
18
tWDD
Write Pulse to Data Delay
INTERRUPT TIMING[19]
Note
18
tWINS
tEINS
tINS
tOINR
tEINR
tINR
R/W to INTERRUPT Set Time
CE to INTERRUPT Set Time
Address to INTERRUPT Set Time
OE to INTERRUPT Reset Time[16]
CE to INTERRUPT Reset Time[16]
Address to INTERRUPT Reset Time[16]
15
15
15
15
15
15
Switching Characteristics Over the Operating Range[6, 11]
7C132-35
7C136-35
7C142-35
7C146-35
Parameter
Description
READ CYCLE
tRC
tAA
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
tPD
Read Cycle Time
Address to Data Valid[12]
Data Hold from Address Change
CE LOW to Data Valid[12]
OE LOW to Data Valid[12]
OE LOW to Low Z[10, 13]
OE HIGH to High Z[10, 13, 14]
CE LOW to Low Z[10, 13]
CE HIGH to High Z[10, 13, 14]
CE LOW to Power-Up[10]
CE HIGH to Power-Down[10]
Min. Max.
35
35
0
35
20
3
20
5
20
0
35
7C132-25[3]
7C136-25
7C142-25
7C146-25
Min. Max.
20
20
20
20
5
0
20
25
Note
18
Note
18
25
25
25
25
25
25
7C132-45
7C136-45
7C142-45
7C146-45
Min. Max.
45
45
0
45
25
3
20
5
20
0
35
7C132-30
7C136-30
7C142-30
7C146-30
Min. Max.
20
20
20
20
5
0
30
30
Note
18
Note
18
25
25
25
25
25
25
7C132-55
7C136-55
7C142-55
7C146-55
Min. Max.
55
55
0
55
25
3
25
5
25
0
35
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
5 Page 
Interrupt Timing Diagrams[19] (continued)
Right Side Sets INTL:
ADDRESS R
CER
tWC
WRITE 7FE
tINS
tHA
R/WR
INTL
tEINS
tSA tWINS
Right Side Clears INTL:
ADDRESSL
CEL
R/WL
OEL
INTL
tEINR
tHA
CY7C132/CY7C136
CY7C142/CY7C146
tRC
READ 7FE
tINR
tOINR
C132-19
C132-20
11
11 Page | ||
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| PDF Descargar | [ Datasheet 7C132-25.PDF ] | |
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