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부품번호 | MAX1126 기능 |
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기능 | Quad / 12-Bit / 40Msps / 1.8V ADC with Serial LVDS Outputs | ||
제조업체 | Maxim Integrated | ||
로고 | |||
전체 25 페이지수
19-3143; Rev 1; 3/04
EVAALVUAAILTAIOBNLEKIT
Quad, 12-Bit, 40Msps, 1.8V ADC with
Serial LVDS Outputs
General Description
The MAX1126 quad, 12-bit analog-to-digital converter
(ADC) features fully differential inputs, a pipelined
architecture, and digital error correction. This ADC is
optimized for low-power, high-dynamic performance for
medical imaging, communications, and instrumentation
applications. The MAX1126 operates from a 1.7V to
1.9V single supply and consumes only 563mW while
delivering a 69.9dB signal-to-noise ratio (SNR) at a
5.3MHz input frequency. In addition to low operating
power, the MAX1126 features an 813µA power-down
mode for idle periods.
An internal 1.24V precision bandgap reference sets the
ADC’s full-scale range. A flexible reference structure
allows the use of an external reference for applications
requiring increased accuracy or a different input volt-
age range.
A single-ended clock controls the conversion process.
An internal duty-cycle equalizer allows for wide varia-
tions in input-clock duty cycle. An on-chip phase-
locked loop (PLL) generates the high-speed serial
low-voltage differential signaling (LVDS) clock.
The MAX1126 provides serial LVDS outputs for data,
clock, and frame alignment signals. The output data is
presented in two’s complement or binary format.
Refer to the MAX1127 data sheet for a pin-compatible
65Msps version of the MAX1126.
The MAX1126 is available in a small, 10mm x 10mm x
0.9mm, 68-pin QFN package with exposed paddle and
is specified for the extended industrial (-40°C to +85°C)
temperature range.
Applications
Ultrasound and Medical Imaging
Positron Emission Tomography (PET) Imaging
Multichannel Communication Systems
Instrumentation
Features
♦ Four ADC Channels with Serial LVDS/SLVS
Outputs
♦ Excellent Dynamic Performance
69.9dB SNR at fIN = 5.3MHz
93.7dBc SFDR at fIN = 5.3MHz
-90dB Channel Isolation
♦ Ultra-Low Power
135mW per Channel (Normal Operation)
1.5mW Total (Shutdown Mode)
♦ Accepts 20% to 80% Clock Duty Cycle
♦ Self-Aligning Data-Clock to Data-Output Interface
♦ Fully Differential Analog Inputs
♦ Wide ±1.4VP-P Differential Input Voltage Range
♦ Internal/External Reference Option
♦ Test Mode for Digital Signal Integrity
♦ LVDS Outputs Support Up to 30in FR-4 Backplane
Connections
♦ Small, 68-Pin QFN with Exposed Paddle
♦ Evaluation Kit Available (MAX1127EVKIT)
Ordering Information
PART
MAX1126EGK
TEMP RANGE
-40°C to +85°C
PIN-PACKAGE
68 QFN 10mm x
x 10mm x 0.9mm
Pin Configuration
68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
GND 1
IN0P 2
IN0N 3
GND 4
IN1P 5
IN1N 6
GND 7
AVDD 8
AVDD 9
AVDD 10
GND 11
IN2P 12
IN2N 13
GND 14
IN3P 15
IN3N 16
GND 17
EP
MAX1126
51 OUT0P
50 OUT0N
49 OVDD
48 OUT1P
47 OUT1N
46 OVDD
45 CLKOUTP
44 CLKOUTN
43 OVDD
42 FRAMEP
41 FRAMEN
40 OVDD
39 OUT2P
38 OUT2N
37 OVDD
36 OUT3P
35 OUT3N
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
QFN
10mm x 10mm x 0.9mm
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Quad, 12-Bit, 40Msps, 1.8V ADC with
Serial LVDS Outputs
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = 1.8V, OVDD = 1.8V, CVDD = 1.8V, GND = 0, external VREFIO = 1.24V, INTREF = AVDD, CREFIO to GND = 0.1µF,
fCLK = 40MHz (50% duty cycle), DT = 0, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
Input Leakage
Input at GND
DIIN
Input at AVDD
Input Capacitance
DCIN
DIGITAL INPUTS (PLL_, LVDSTEST, DT, SLVS/LVDS, PD_, PDALL, T/B)
Input High Threshold
VIH
MIN TYP
5
0.8 x
AVDD
Input Low Threshold
VIL
Input at GND, except PLL2 and PLL3
Input Leakage
DIIN Input at AVDD, except PLL2 and PLL3
PLL2 and PLL3 only
Input Capacitance
DCIN
LVDS OUTPUTS (OUT_P, OUT_N, SLVS/LVDS = 0
5
Differential Output Voltage
VOHDIFF RTERM = 100Ω
250
Output Common-Mode Voltage
VOCM RTERM = 100Ω
1.125
Rise Time (20% to 80%)
tR RTERM = 100Ω, CLOAD = 5pF
150
Fall Time (80% to 20%)
tF RTERM = 100Ω, CLOAD = 5pF
150
SLVS OUTPUTS (OUT_P, OUT_N, CLKOUTP, CLKOUTN, FRAMEP, FRAMEN), SLVS/LVDS = 1, DT = 1
Differential Output Voltage
VOHDIFF RTERM = 100Ω
240
Output Common-Mode Voltage
Rise Time (20% to 80%)
VOCM
tR
RTERM = 100Ω
RTERM = 100Ω, CLOAD = 5pF
220
120
Fall Time (80% to 20%)
tF RTERM = 100Ω, CLOAD = 5pF
120
POWER-DOWN
PD Fall to Output Enable
tENABLE
132
PD Rise to Output Disable
tDISABLE
10
POWER REQUIREMENTS
AVDD Supply Voltage
AVDD
1.7 1.8
OVDD Supply Voltage
OVDD
1.7 1.8
CVDD Supply Voltage
CVDD
1.7 1.8
MAX
5
80
UNITS
µA
pF
0.2 x
AVDD
5
80
200
V
V
µA
pF
450
1.375
mV
V
ps
ps
mV
mV
ps
ps
µs
ns
1.9 V
1.9 V
3.6 V
4 _______________________________________________________________________________________
4페이지 Quad, 12-Bit, 40Msps, 1.8V ADC with
Serial LVDS Outputs
Typical Operating Characteristics
(AVDD = 1.8V, OVDD = 1.8V, CVDD = 1.8V, GND = 0, external VREFIO = 1.24V, INTREF = AVDD, differential input at -0.5dBFS,
fCLK = 40MHz (50% duty cycle), DT = low, CLOAD = 10pF, TA = +25°C, unless otherwise noted.)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
0
FFT PLOT
(32,768-POINT DATA RECORD)
fCLK = 40.96MHz
fIN = 5.30125MHz
AIN = -0.5dBFS
SNR = 69.88dB
SINAD = 69.85dB
THD = -91.46dBc
SFDR = 93.65dBc
HD2 HD3
4 8 12 16
FREQUENCY (MHz)
20
FFT PLOT
(32,768-POINT DATA RECORD)
0
-10
fCLK = 40.96MHz
fIN = 19.00125MHz
-20 AIN = -0.5dBFS
-30 SNR = 69.20dB
-40 SINAD = 69.16dB
THD = -88.74dBc
-50 SFDR = 89.04dBc
-60
-70
HD3
-80 HD2
-90
-100
-110
-120
0 4 8 12 16
FREQUENCY (MHz)
20
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
0
CROSSTALK
(4096-POINT DATA RECORD)
MEASURED ON CHANNEL 2,
WITH INTERFERING SIGNAL
ON CHANNEL 0
fCLK = 39.9997651MHz
fIN(IN2) = 5.2831721MHz
fIN(IN0) = 19.3260584MHz
4 8 12 16
FREQUENCY (MHz)
20
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
0
CROSSTALK
(4096-POINT DATA RECORD)
MEASURED ON CHANNEL 2,
WITH INTERFERING SIGNAL
ON CHANNEL 1
fCLK = 39.9997651MHz
fIN(IN2) = 5.2831721MHz
fIN(IN1) = 19.3260584MHz
4 8 12 16
FREQUENCY (MHz)
20
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
0
CROSSTALK
(4096-POINT DATA RECORD)
MEASURED ON CHANNEL 2,
WITH INTERFERING SIGNAL
ON CHANNEL 3
fCLK = 39.9997651MHz
fIN(IN2) = 5.2831721MHz
fIN(IN3) = 19.3260584MHz
4 8 12 16
FREQUENCY (MHz)
20
TWO-TONE INTERMODULATION DISTORTION
(32,768-POINT DATA RECORD)
0
-10
fIN(IN1) = 12.40125MHz
fIN(IN2) = 13.60125MHz
-20 AIN1 = -6.5dBFS
-30 AIN2 = -6.5dBFS
-40 IMD = 87.0dBc
IM3 = 89.3dBc
-50
-60
-70
-80
-90
-100
-110
-120
0 4 8 12 16 20
FREQUENCY (MHz)
GAIN BANDWIDTH PLOT
1
FULL-POWER
BANDWIDTH
0 -0.5dBFS
-1 SMALL-SIGNAL
BANDWIDTH
-2 -20dBFS
-3
-4 LIMITED BY
MAX1127EVKIT
INPUT CIRCUITRY
-5
1 10
100
ANALOG INPUT FREQUENCY (MHz)
1000
_______________________________________________________________________________________ 7
7페이지 | |||
구 성 | 총 25 페이지수 | ||
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