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MAX1127 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 MAX1127
기능 Quad / 12-Bit / 65Msps / 1.8V ADC with Serial LVDS Outputs
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MAX1127 데이터시트, 핀배열, 회로
19-3144; Rev 1; 3/04
Quad, 12-Bit, 65Msps, 1.8V ADC with
Serial LVDS Outputs
General Description
The MAX1127 quad, 12-bit analog-to-digital converter
(ADC) features fully differential inputs, a pipelined
architecture, and digital error correction. This ADC is
optimized for low-power, high-dynamic performance for
medical imaging, communications, and instrumentation
applications. The MAX1127 operates from a 1.7V to
1.9V single supply and consumes only 563mW while
delivering a 69.6dB signal-to-noise ratio (SNR) at a
19.3MHz input frequency. In addition to low operating
power, the MAX1127 features a 675µA power-down
mode for idle periods.
An internal 1.24V precision bandgap reference sets the
ADC’s full-scale range. A flexible reference structure
allows the use of an external reference for applications
requiring increased accuracy or a different input volt-
age range.
A single-ended clock controls the conversion process.
An internal duty-cycle equalizer allows for wide varia-
tions in input-clock duty cycle. An on-chip phase-
locked loop (PLL) generates the high-speed serial
low-voltage differential signaling (LVDS) clock.
The MAX1127 provides serial LVDS outputs for data,
clock, and frame alignment signals. The output data is
presented in two’s complement or binary format.
Refer to the MAX1126 data sheet for a pin-compatible
40Msps version of the MAX1127.
The MAX1127 is available in a small, 10mm x 10mm x
0.9mm, 68-pin QFN package with exposed paddle and
is specified for the extended industrial (-40°C to +85°C)
temperature range.
Applications
Ultrasound and Medical Imaging
Positron Emission Tomography (PET) Imaging
Multichannel Communication Systems
Instrumentation
Features
Four ADC Channels with Serial LVDS/SLVS
Outputs
Excellent Dynamic Performance
69.6dB SNR at fIN = 19.3MHz
92dBc SFDR at fIN = 19.3MHz
-87dB Channel Isolation
Ultra-Low Power
135mW per Channel (Normal Operation)
1.2mW Total (Shutdown Mode)
Accepts 20% to 80% Clock Duty Cycle
Self-Aligning Data-Clock to Data-Output Interface
Fully Differential Analog Inputs
Wide ±1.4VP-P Differential Input Voltage Range
Internal/External Reference Option
Test Mode for Digital Signal Integrity
LVDS Outputs Support Up to 30in FR-4 Backplane
Connections
Small, 68-Pin QFN with Exposed Paddle
Evaluation Kit Available (MAX1127EVKIT)
Ordering Information
PART
MAX1127EGK
TEMP RANGE
-40°C to +85°C
PIN-PACKAGE
68 QFN 10mm x
x 10mm x 0.9mm
Pin Configuration
68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
GND 1
IN0P 2
IN0N 3
GND 4
IN1P 5
IN1N 6
GND 7
AVDD 8
AVDD 9
AVDD 10
GND 11
IN2P 12
IN2N 13
GND 14
IN3P 15
IN3N 16
GND 17
EP
MAX1127
51 OUT0P
50 OUT0N
49 OVDD
48 OUT1P
47 OUT1N
46 OVDD
45 CLKOUTP
44 CLKOUTN
43 OVDD
42 FRAMEP
41 FRAMEN
40 OVDD
39 OUT2P
38 OUT2N
37 OVDD
36 OUT3P
35 OUT3N
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
QFN
10mm x 10mm x 0.9mm
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.




MAX1127 pdf, 반도체, 판매, 대치품
Quad, 12-Bit, 65Msps, 1.8V ADC with
Serial LVDS Outputs
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = 1.8V, OVDD = 1.8V, CVDD = 1.8V, GND = 0, external VREFIO = 1.24V, INTREF = AVDD, CREFIO to GND = 0.1µF,
fCLK = 65MHz (50% duty cycle), DT = 0, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
Input Leakage
Input at GND
DIIN Input at AVDD
Input Capacitance
DCIN
DIGITAL INPUTS (PLL_, LVDSTEST, DT, SLVS/LVDS, PD_, PDALL, T/B)
Input High Threshold
VIH
MIN TYP
5
0.8 x
AVDD
Input Low Threshold
VIL
Input at GND, except PLL2 and PLL3
Input Leakage
DIIN Input at AVDD, except PLL2 and PLL3
PLL2 and PLL3 only
Input Capacitance
DCIN
LVDS OUTPUTS (OUT_P, OUT_N, SLVS/LVDS = 0)
5
Differential Output Voltage
VOHDIFF RTERM = 100
250
Output Common-Mode Voltage
VOCM RTERM = 100
1.125
Rise Time (20% to 80%)
tR RTERM = 100, CLOAD = 5pF
150
Fall Time (80% to 20%)
tF RTERM = 100, CLOAD = 5pF
150
SLVS OUTPUTS (OUT_P, OUT_N, CLKOUTP, CLKOUTN, FRAMEP, FRAMEN), SLVS/LVDS = 1, DT = 1
Differential Output Voltage
VOHDIFF RTERM = 100
240
Output Common-Mode Voltage
Rise Time (20% to 80%)
VOCM
tR
RTERM = 100
RTERM = 100, CLOAD = 5pF
220
120
Fall Time (80% to 20%)
POWER-DOWN
tF RTERM = 100, CLOAD = 5pF
120
PD Fall to Output Enable
PD Rise to Output Disable
tENABLE
tDISABLE
132
10
POWER REQUIREMENTS
AVDD Supply Voltage
AVDD
1.7 1.8
OVDD Supply Voltage
OVDD
1.7 1.8
CVDD Supply Voltage
CVDD
1.7 1.8
MAX
5
80
UNITS
µA
pF
0.2 x
AVDD
5
80
200
V
V
µA
pF
450
1.375
mV
V
ps
ps
mV
mV
ps
ps
µs
ns
1.9 V
1.9 V
3.6 V
4 _______________________________________________________________________________________

4페이지










MAX1127 전자부품, 판매, 대치품
Quad, 12-Bit, 65Msps, 1.8V ADC with
Serial LVDS Outputs
Typical Operating Characteristics
(AVDD = 1.8V, OVDD = 1.8V, CVDD = 1.8V, GND = 0, external VREFIO = 1.24V, INTREF = AVDD, differential input at -0.5dBFS,
fCLK = 65MHz (50% duty cycle), DT = low, CLOAD = 10pF, TA = +25°C, unless otherwise noted.)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
0
FFT PLOT
(32,768-POINT DATA RECORD)
fCLK = 65.04448MHz
fIN = 5.301935MHz
AIN = -0.5dBFS
SNR = 69.5dB
SINAD = 69.47dB
THD = -90.94dBc
SFDR = 93.27dBc
HD2 HD3
4 8 12 16 20 24 28 32
FREQUENCY (MHz)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
0
FFT PLOT
(32,768-POINT DATA RECORD)
fCLK = 65.04448MHz
fIN = 30.30301MHz
AIN = -0.5dBFS
SNR = 69.45dB
SINAD = 69.4dB
THD = -89.3dBc
SFDR = 89.7dBc
HD3
HD2
4 8 12 16 20 24 28 32
FREQUENCY (MHz)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
0
CROSSTALK
(4096-POINT DATA RECORD)
MEASURED ON CHANNEL 1,
WITH INTERFERING SIGNAL
ON CHANNEL 0.
fIN(IN1) = 5.3489349MHz
fIN(IN0) = 30.2683055MHz
4 8 12 16 20 24 28 32
FREQUENCY (MHz)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
0
CROSSTALK
(4096-POINT DATA RECORD)
MEASURED ON CHANNEL 1,
WITH INTERFERING SIGNAL
ON CHANNEL 2.
fIN(IN1) = 5.3489349MHz
fIN(IN2) = 30.2683055MHz
4 8 12 16 20 24 28 32
FREQUENCY (MHz)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
0
CROSSTALK
(4096-POINT DATA RECORD)
MEASURED ON CHANNEL 1,
WITH INTERFERING SIGNAL
ON CHANNEL 3.
fIN(IN1) = 5.3489349MHz
fIN(IN3) = 30.2683055MHz
4 8 12 16 20 24 28 32
FREQUENCY (MHz)
TWO-TONE INTERMODULATION DISTORTION
(32,768-POINT DATA RECORD)
0
-10
fIN(IN1) = 12.348685MHz
fIN(IN2) = 13.650845MHz
-20 AIN1 = -6.5dBFS
-30 AIN2 = -6.5dBFS
-40 IMD = 91.2dBc
IM3 = 95.7dBc
-50
-60
-70
-80
-90
-100
-110
-120
0 4 8 12 16 20 24 28 32
FREQUENCY (MHz)
GAIN BANDWIDTH PLOT
1
SMALL-SIGNAL
0 BANDWIDTH
-20dBFS
-1
FULL-POWER
-2 BANDWIDTH
-0.5dBFS
-3
-4
-5
LIMITED BY
-6 MAX1127EVKIT
INPUT CIRCUITRY
-7
1 10
100
ANALOG INPUT FREQUENCY (MHz)
1000
_______________________________________________________________________________________ 7

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