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7C199-25 데이터시트 PDF




Cypress Semiconductor에서 제조한 전자 부품 7C199-25은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 7C199-25 자료 제공

부품번호 7C199-25 기능
기능 32K x 8 Static RAM
제조업체 Cypress Semiconductor
로고 Cypress Semiconductor 로고


7C199-25 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.




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7C199-25 데이터시트, 핀배열, 회로
CY7C199
Features
• High speed
— 10 ns
• Fast tDOE
• CMOS for optimum speed/power
• Low active power
— 467 mW (max, 12 ns “L” version)
• Low standby power
— 0.275 mW (max, “L” version)
• 2V data retention (“L” version only)
• Easy memory expansion with CE and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
Functional Description
The CY7C199 is a high-performance CMOS static RAM
organized as 32,768 words by 8 bits. Easy memory expansion
Logic Block Diagram
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
CE
WE
OE
INPUT BUFFER
1024 x 32 x 8
ARRAY
COLUMN
DECODER
POWER
DOWN
32K x 8 Static RAM
is provided by an active LOW Chip Enable (CE) and active
LOW Output Enable (OE) and three-state drivers. This device
has an automatic power-down feature, reducing the power
consumption by 81% when deselected. The CY7C199 is in the
standard 300-mil-wide DIP, SOJ, and LCC packages.
An active LOW Write Enable signal (WE) controls the
writing/reading operation of the memory. When CE and WE
inputs are both LOW, data on the eight data input/output pins
(I/O0 through I/O7) is written into the memory location
addressed by the address present on the address pins (A0
through A14). Reading the device is accomplished by selecting
the device and enabling the outputs, CE and OE active LOW,
while WE remains inactive or HIGH. Under these conditions,
the contents of the location addressed by the information on
address pins are present on the eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and Write Enable
(WE) is HIGH. A die coat is used to improve alpha immunity.
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
Pin Configurations
DIP / SOJ / SOIC
Top View
LCC
Top View
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 VCC
27 WE
26 A4
25 A3
24 A2
23 A1
22 OE
21 A0
20 CE
19 I/O7
18 I/O6
17 I/O5
16 I/O4
15 I/O3
3 2 1 28 27
A8 4
A9 5
26 A4
25 A3
A10 6
A11 7
A12 8
24 A2
23 A1
22 OE
A13 9
A14 10
21 A0
20 CE
I/O0 11
19 I/O7
I/O1 12
18 I/O6
1314151617
OE
A1
A2
A3
A4
WE
V CC
A5
A6
A7
A8
A9
A 10
A 11
22
23
24
25
26
27
28
1
2
3
4
5
6
7
TSOP I
Top View
(not to scale)
21 A 0
20 CE
19 I/O 7
18 I/O 6
17 I/O 5
16 I/O 4
15 I/O 3
14 GND
13 I/O 2
12 I/O 1
11 I/O 0
10 A 14
9 A 13
8 A 12
Selection Guide
Maximum Access Time
Maximum Operating Current
L
Maximum CMOS Standby Current
L
Shaded area contains advance information.
7C199
-8
8
120
0.5
7C199
-10
10
110
90
0.5
0.05
7C199
-12
12
160
90
10
0.05
7C199
-15
15
155
90
10
0.05
7C199
-20
20
150
90
10
0.05
7C199
-25
25
150
80
10
0.05
7C199
-35
35
140
70
10
0.05
7C199
-45
45
140
Unit
ns
mA
10 mA
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-05160 Rev. *A
Revised January 7, 2003




7C199-25 pdf, 반도체, 판매, 대치품
CY7C199
Switching Characteristics Over the Operating Range (-8, -10, -12, -15) [3, 7]
Parameter
Description
Read Cycle
tRC Read Cycle Time
tAA Address to Data Valid
tOHA
Data Hold from Address Change
tACE CE LOW to Data Valid
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
OE LOW to Data Valid
OE LOW to Low-Z[8]
OE HIGH to High-Z[8, 9]
CE LOW to Low-Z[8]
CE HIGH to High-Z[8,9]
tPU CE LOW to Power-up
tPD CE HIGH to Power-down
Write Cycle[10, 11]
tWC
tSCE
tAW
tHA
tSA
tPWE
tSD
tHD
tHZWE
tLZWE
Write Cycle Time
CE LOW to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
Data Set-up to Write End
Data Hold from Write End
WE LOW to High-Z[9]
WE HIGH to Low-Z[8]
7C199-8
7C199-10
7C199-12
7C199-15
Min. Max. Min. Max. Min. Max. Min. Max. Unit
8 10 12 15 ns
8 10 12 15 ns
3 3 3 3 ns
8 10 12 15 ns
4.5 5 5 7 ns
0 0 0 0 ns
5 5 5 7 ns
3 3 3 3 ns
4 5 5 7 ns
0 0 0 0 ns
8 10 12 15 ns
8 10 12 15 ns
7 7 9 10 ns
7 7 9 10 ns
0 0 0 0 ns
0 0 0 0 ns
7 7 8 9 ns
5 5 8 9 ns
0 0 0 0 ns
5 6 7 7 ns
3 3 3 3 ns
Switching Characteristics Over the Operating Range (-20, -25, -35, -45)[3, 7]
7C199-20
7C199-25
7C199-35
7C199-45
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Unit
Read Cycle
tRC Read Cycle Time
20 25 35 45
ns
tAA Address to Data Valid
20 25 35 45 ns
tOHA
Data Hold from Address Change 3
3
3
3
ns
tACE CE LOW to Data Valid
20 25 35 45 ns
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
OE LOW to Data Valid
OE LOW to Low-Z[8]
OE HIGH to High-Z[8, 9]
CE LOW to Low-Z[8]
CE HIGH to High-Z[8, 9]
9 10 16 16 ns
0 0 0 0 ns
9 11 15 15 ns
3 3 3 3 ns
9 11 15 15 ns
tPU CE LOW to Power-up
0
0
0
0
ns
Shaded area contains advance information.
Notes:
7. Test conditions assume signal transition time of 3 ns or less for -12 and -15 speeds and 5 ns or less for -20 and slower speeds, timing reference levels of 1.5V,
input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance.
8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
9. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
10. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
11. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document #: 38-05160 Rev. *A
Page 4 of 13

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7C199-25 전자부품, 판매, 대치품
CY7C199
Typical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.4
1.2
1.0 ICC
0.8
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
1.4
ICC
1.2
1.0
0.8
0.6 VIN =5.0V
TA =25°C
0.4
0.2 ISB
0.0
4.0 4.5 5.0 5.5
SUPPLY VOLTAGE (V)
6.0
0.6
0.4
0.2
0.0
55
VCC =5.0V
VIN =5.0V
ISB
25 125
AMBIENT TEMPERATURE (°C)
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
1.4
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
1.6
1.3
1.2
1.1
1.0
0.9
0.8
4.0
TA =25°C
4.5 5.0 5.5 6.0
SUPPLY VOLTAGE (V)
1.4
1.2
1.0
VCC =5.0V
0.8
0.6
55
25
125
AMBIENT TEMPERATURE (°C)
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
120
100
80
60
VCC =5.0V
TA =25°C
40
20
0
0.0 1.0 2.0 3.0 4.0
OUTPUT VOLTAGE (V)
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
140
120
100
80
60 VCC =5.0V
40 TA =25°C
20
0
0.0
1.0 2.0 3.0
OUTPUT VOLTAGE (V)
4.0
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0.0
1.0 2.0 3.0 4.0 5.0
SUPPLY VOLTAGE (V)
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
30.0
25.0
20.0
15.0
10.0
5.0
VCC =4.5V
TA =25°C
0.0
0
200 400 600 800 1000
CAPACITANCE (pF)
NORMALIZED ICC vs. CYCLE TIME
1.25
1.00
VCC =5.0V
TA =25°C
VIN =0.5V
0.75
0.50
10
20 30 40
CYCLE FREQUENCY (MHz)
Truth Table
CE WE
HX
LH
LL
LH
OE Inputs/Outputs
X High Z
L Data Out
X Data In
H High Z
Mode
Deselect/Power-down
Read
Write
Deselect, Output disabled
Power
Standby (ISB)
Active (ICC)
Active (ICC)
Active (ICC)
Document #: 38-05160 Rev. *A
Page 7 of 13

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7C199-25

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