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부품번호 | 7LVC373APWDH 기능 |
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기능 | Octal D-type transparent latch with 5-volt tolerant inputs/outputs 3-State | ||
제조업체 | NXP Semiconductors | ||
로고 | |||
INTEGRATED CIRCUITS
74LVC373A
Octal D-type transparent latch with 5-volt
tolerant inputs/outputs (3-State)
Product specification
1998 Jul 29
Philips
Semiconductors
Philips Semiconductors
Octal D-type transparent latch with 5-volt
tolerant inputs/outputs (3-State)
Product specification
74LVC373A
LOGIC DIAGRAM
D0 D1 D2 D3 D4 D5 D6 D7
DQ
LE LE
DQ
LE LE
DQ
LE LE
DQ
LE LE
DQ
LE LE
DQ
LE LE
DQ
LE LE
DQ
LE LE
LE
OE
Q0 Q1 Q2 Q3 Q4 Q5
FUNCTION TABLE
OPERATING MODES
Enable and read register
(transparent mode)
INPUTS
OE LE Dn
LHL
L HH
Latch and read register
L
L
l
LLh
Latch register and
disable outputs
HL
l
HL h
H = HIGH voltage level
h = HIGH voltage level one setup time prior to the HIGH-to-LOW LE transition
L = LOW voltage level
l = LOW voltage level one setup time prior to the HIGH-to-LOW LE transition
X = Don’t care
Z = High impedance OFF-state
INTERNAL LATCHES
L
H
L
H
L
H
Q6 Q7
SA00386
OUTPUTS
Q0 to Q7
L
H
H
H
Z
Z
1998 Jul 29
4
4페이지 Philips Semiconductors
Octal D-type transparent latch with 5-volt
tolerant inputs/outputs (3-State)
Product specification
74LVC373A
AC CHARACTERISTICS
GND = 0V; tr = tf v 2.5ns; CL = 50pF; RL = 500Ω; Tamb = –40°C to +85°C.
SYMBOL
PARAMETER
WAVEFORM
VCC = 3.3V ±0.3V
MIN TYP1 MAX
tPHL
tPLH
tPHL
tPLH
tPZH
tPZL
tPHZ
tPLZ
Propagation delay
Dn to Qn
Propagation delay
LE to Qn
3-State output enable time
OE to Qn
3-State output disable time
OE to Qn
1, 5 1.5 4.2 6.8
2, 5 1.5 4.6 7.2
3, 5 1.5 4.8 7.7
3, 5 1.5 4.3 6.1
tW LE pulse width HIGH
2 3.0 1.5
tSU
Setup time
Dn to LE
4 2.0 0
th
Hold time
Dn to LE
4 1.5 0.3
NOTE:
1. Unless otherwise stated, all typical values are at VCC = 3.3V and Tamb = 25°C.
–
–
–
LIMITS
VCC = 2.7V
MIN MAX
1.5 7.8
1.5 8.2
1.5 8.7
1.5 7.1
3.0 –
2.0 –
1.5 –
VCC = 1.2V
TYP
19
21
22
15
–
–
–
UNIT
ns
ns
ns
ns
ns
ns
ns
AC WAVEFORMS
VM = 1.5V at VCC w 2.7V; VM = 0.5 VCC at VCC t 2.7V.
VOL and VOH are the typical output voltage drop that occur with the
output load.
VX = VOL + 0.3V at VCC w 2.7V; VX = VOL + 0.1 VCC at VCC t 2.7V
VY = VOH –0.3V at VCC w 2.7V; VY = VOH – 0.1 VCC at VCC t 2.7V
VI
INPUT
VM
GND
VOH
tPHL
tPLH
OUTPUT
VM
VOL
SY00041
Waveform 1. Input (Dn) to output (Qn) propagation delays.
VI
LE INPUT
GND
VOH
Qn OUTPUT
VOL
VM
tw
tPHL
VM
tPLH
SA00388
Waveform 2. Latch enable input (LE) pulse width, the latch
enable input to output (Qn) propagation delays
VI
nOE INPUT
GND
VM
VCC
Qn OUTPUT
LOW-to-OFF
OFF-to-LOW
VOL
VOH
Qn OUTPUT
HIGH-to-OFF
OFF-to-HIGH
GND
tPLZ
tPZL
tPHZ
VX
VY
tPZH
outputs
enabled
outputs
disabled
Waveform 3. 3-State enable and disable times.
VM
VM
outputs
enabled
SW00207
1998 Jul 29
7
7페이지 | |||
구 성 | 총 12 페이지수 | ||
다운로드 | [ 7LVC373APWDH.PDF 데이터시트 ] |
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구매 문의 | 일반 IC 문의 : 샘플 및 소량 구매 ----------------------------------------------------------------------- IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한 광범위한 전력 반도체를 판매합니다. 전력 반도체 전문업체 상호 : 아이지 인터내셔날 사이트 방문 : [ 홈페이지 ] [ 블로그 1 ] [ 블로그 2 ] |
부품번호 | 상세설명 및 기능 | 제조사 |
7LVC373APWDH | Octal D-type transparent latch with 5-volt tolerant inputs/outputs 3-State | NXP Semiconductors |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |