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MK1491-06STR 데이터시트 PDF




Integrated Circuit Systems에서 제조한 전자 부품 MK1491-06STR은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 MK1491-06STR 자료 제공

부품번호 MK1491-06STR 기능
기능 CS5530 Geode Clock Source
제조업체 Integrated Circuit Systems
로고 Integrated Circuit Systems 로고


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MK1491-06STR 데이터시트, 핀배열, 회로
Description
The MK1491-06 is a low cost, low jitter, high
performance clock synthesizer for National
Semiconductor CS5530 based computer and
portable appliance applications. Using patented
analog Phase-Locked Loop (PLL) techniques,
the device accepts a 14.318 MHz crystal input to
produce multiple output clocks. It provides
selectable PCI local bus and AC97 audio clocks,
24 MHz and 48 MHz clocks for Super I/O and
USB, as well as multiple Reference outputs.
The device has multiple power down modes to
reduce power consumption.
MK1491-06
CS5530 GeodeClock Source
Features
• Packaged in 28 pin, 300 mil wide SOIC or in
28 pin, 150 mil wide SSOP
• Provides all critical timing for the National
Semiconductor CS5530 Geode companion chip
• Four PCI clocks
• Selectable PCIF on up to 2 outputs
• Early PCI clock selectability
• Up to 4 Reference clocks
• 48 MHz USB and 24MHz SIO support
• AC97 audio clock
• Multiple power down modes
• Low EMI Enable pin reduces EMI radiation on
PCI clocks (patented)
• 3.3 V ±5% operation
Block Diagram
PCI Frequency Select
Low EMI Enable
PCIF Function Enable
Early PCI Enable
SLOW#
PCISTP#
PWRDWN#
Audio Select
VDD
6
2
14.3M/24M Select
XI
14.31818 MHz
crystal
XO
Crystal
Oscillator
GND
5
PCI
Clocks
Output
Buffers
Output
Buffer
3
PCI
EPCI/PCI
Audio
Clock
Fixed
Clocks
MUX
Output
Buffer
Output
Buffer
16.934 MHz or
24.576 MHz or
49.152 MHz
48 MHz
Output
Buffer
14.318 MHz or
24 MHz
Output
Buffers
3
14.318 MHz
MDS 1491-06 F
1 Revision 101700 Printed 11/15/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel • www.icst.com




MK1491-06STR pdf, 반도체, 판매, 대치품
MK1491-06
CS5530 GeodeClock Source
Power Down Control Table
PCISTP# PWRDWN# SLOW#
X 0X
0 1X
1 1X
MODE
Power Down
PCI STOP
ON
PCI
LOW
LOW
ON
PCIF
LOW
ON
ON
24/14.3 14.3 DESCRIPTION
LOW LOW All outputs low. PLLs and Oscillator off.
ON ON PCI clocks synchronously enter and leave low state.
ON ON All Clocks On.
Key: 1 = connected to VDD, 0 = connected to ground, X = any valid logic level, Combination Input/Outputs should be connected to VDD or
Ground through a 10 kresistor as shown below.
Power-On Default Conditions
Input Pin#
5
8
10
12
13
15
16
21
22
28
Function
TS
SEL AUDIO
SLOW#
FS
SEL24
PWRDWN#
PCISTP#
LE#
EPCI#
PEN
Default Condition
M All outputs enabled.
M Audio clock (pin 28) set to 24.576 MHz
1 PCI clocks set to 33.3 MHz. Refer to Power Down Control Table above.
1 PCI frequency = 33.3 MHz.
1 24M/14.3M (pin 19) set to 24 MHz.
1 All clocks running.
1 PCI clocks running.
1 Low EMI function OFF
1 Pin 22 set to normal PCI signal (not early).
M PCI (pin 25) set to PCI clock (33.33 MHz). PCI (pin 24) set to PCIF clock (33.33 MHz).
External Components
The MK1491-06 requires some inexpensive external components for proper operation. Decoupling capacitors of 0.1µF should be
connected on each VDD pin to ground, as close to the MK1491-06 as possible. A series termination resistor of 33may be used for
each clock output. See the discussion below for other external resistors required for proper I/O operation. The 14.3 MHz oscillator
has internal caps that provide the proper load for a parallel resonant crystal with CL=18 pF. For tuning with other values of CL, the
formula 2*(CL-18) gives the value of each capacitor that should be connected between X1 and ground and X2 and ground.
I/O Structure
The MK1491-06 provides more functionality in a 28 pin package by using
a unique I/O technique. The device checks the status of all I/O pins
during power-up and at exit from the Power Down state. This status
(pulled high, low, or mid-level) then determines the frequency selections
and power down modes (see the tables on pages 2 and 4). Within 10ms
after power up, the inputs change to outputs and the clocks start up. In the
diagrams to the right, the 33resistors are the normal output
termination resistors. The 10kresistor pulls low to generate a logic
zero. Weak internal pull-up resistors are present on SEL24, EPCI#, FS,
LE#, PCISTP#, and SLOW#. These pins should be connected directly to
VDD or GND if not under active control. Internal resistors on PEN, SEL
AUDIO, and TS pull to a mid-level (M).
For select
= 0 (low)
33
I/O
to load*
10k
Don’t stuff for
“1” selection
*Note: Do not use a TTL load. This will
overcome the 10 kpulldown and force the
input to a logic 1.
MDS 1491-06 F
4 Revision 101700 Printed 11/15/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel • www.icst.com

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