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MK1574-01SITR 데이터시트 PDF




Integrated Circuit Systems에서 제조한 전자 부품 MK1574-01SITR은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

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부품번호 MK1574-01SITR 기능
기능 Frame Rate Communications PLL
제조업체 Integrated Circuit Systems
로고 Integrated Circuit Systems 로고


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MK1574-01SITR 데이터시트, 핀배열, 회로
I CR O C LOC K
MK1574
Frame Rate Communications PLL
Description
The MK1574-01 is a Phase-Locked Loop (PLL)
based clock synthesizer, which accepts an 8 kHz
clock input as a reference, and generates many
popular communications frequencies. All outputs
are frequency locked together and to the input.
This allows for the generation of locked clocks to
the 8 kHz backplane clock, simplifying clock
generation and distribution in communications
systems.
MicroClock can customize this device for any
other different frequencies.
Features
• Packaged in 16 pin narrow (150 mil) SOIC
• Exact multiplications stored in the device eliminate
the need for external dividers
• Accepts 8 kHz input clock
• Output clock rates include T1, E1, T2, E2
• 3.0V to 5.5V operation
• Available in commercial (0 to +70 C) or industrial
(-40 to +85 C) temperature ranges
• For jitter attenuation, use the MK2049
Block Diagram
VDD GND
22
FS0-3
4
8kHz
Input Clock
Input
Buffer
PLL
Clock
Synthesis
and
Control
Circuitry
Output
Buffer
Output
Buffer
Output
Buffer
Output
Buffer
CAP1
CAP2
CLK1
CLK2
CLK3
8kHz
(recovered)
MDS 1574-01 D
1
Revision 011999
Printed 11/15/00
MicroClock Division of ICS • 525 Race Street • San Jose • CA • 95126•(408)295-9800tel•(408)295-9818fax




MK1574-01SITR pdf, 반도체, 판매, 대치품
I CR O C LOC K
MK1574
Frame Rate Communications PLL
Loop Bandwidth and Loop Filter Component Selection
The series-connected capacitor and resistor between CAP1 and CAP2 (pins 4 and 6) determine the dynamic
characteristics of the phase-locked loop. The capacitor must have very low leakage, therefore a high quality
ceramic capacitor is recommended. DO NOT use any type of polarized or electrolytic capacitor. The series
connected capacitor and resistor between CAP1 and CAP2 (pins 4 and 6) determine the dynamic
characteristics of the phase-locked loop. The capacitor must have very low leakage, therefore a high quality
ceramic capacitor is recommended. DO NOT use any type of polarized or electrolytic capacitor. Ceramic
capacitors should have C0G or NP0 dielectric. Avoid high-K dielectrics like Z5U and X7R; these and other
ceramics which have piezoelectric properties allow mechanical vibration in the system to increase the output
jitter because the mechanical energy is converted directly to voltage noise on the VCO input.
The values of the RC network determine the bandwidth of the PLL. The values of the loop filter components
are calculated using the constants K1 and K2 from the table on page 5. The loop bandwidth is set by the
capacitor C and the constant K1 using the formula
K1
BW (Hz) =
C
Equation 1
The loop damping is set by the resistor R, the capacitor C, and the constant K2 using the formula
ζ • K2
R=
C
Equation 2; ζ (zeta) is the damping factor
For example, to design the loop filter when generating 8.192 MHz from 8 kHz:
1. From the table on page 2, the address is E. The table on page 5 shows constants K1=0.0516 and K2=6.2.
2. A good value for the loop bandwidth is 1/20 the input frequency; where 8 kHz/20 = 400 Hz. Using
Equation 1,
0.0516
400 =
C
Therefore,
( )0.0516 2
C = = 16.6 nF (16 nF nearest standard value)
400
3. A good value for the damping factor ζ is 0.707. From Equation 2,
0.707 • 6.2
R = 16E-9 = 34.7 k(36 knearest standard value)
MDS 1574-01 D
4
Revision 011999
Printed 11/15/00
MicroClock Division of ICS • 525 Race Street • San Jose • CA • 95126•(408)295-9800tel•(408)295-9818fax

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관련 데이터시트

부품번호상세설명 및 기능제조사
MK1574-01SITR

Frame Rate Communications PLL

Integrated Circuit Systems
Integrated Circuit Systems

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