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부품번호 | MK2049-02 기능 |
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기능 | Communications Clock PLLs | ||
제조업체 | Integrated Circuit Systems | ||
로고 | |||
전체 12 페이지수
MK2049-02/03
Communications Clock PLLs
Description
The MK2049-02 and MK2049-03 are Phase-
Locked Loop (PLL) based clock synthesizers that
accept multiple input frequencies. With an 8 kHz
clock input as a reference, the MK2049-02/03
generate T1, E1, T3, E3, ISDN, xDSL, and other
communications frequencies. This allows for the
generation of clocks frequency-locked and phase-
locked to an 8 kHz backplane clock, simplifying
clock synchronization in communications systems.
The MK2049-02/03 can also accept a T1, E1, T3,
or E3 input clock and provide the same output for
loop timing. All outputs are frequency-locked
together and to the input.
These parts also have a jitter-attenuated buffer
capability. In this mode, the MK2049-02/03 are
ideal for filtering jitter from 27 MHz video clocks
or other clocks with high jitter.
ICS/MicroClock can customize these devices for
many other different frequencies. Contact your
ICS/MicroClock representative for more details.
Features
• Packaged in 20 pin SOIC
• Fixed input-output phase relationship on most
clock selections
• Meets the TR62411, ETS300 011, and GR-1244
specification for MTIE, Pull-in/Hold-in Range,
Phase Transients, and Jitter Generation for
Stratum 3, 4, and 4E
• Accept multiple inputs: 8 kHz backplane clock,
Loop Timing frequencies, or 10-28 MHz
• Lock to 8 kHz ±100 ppm (External mode)
• Buffer Mode allows jitter attenuation of
10–28 MHz input and x1/x0.5 or x2/x4 outputs
• Exact internal ratios enable zero ppm error
• Output clock rates include T1, E1, T3, E3, ISDN,
xDSL, and OC3 submultiples
• 5 V ±5% operation. Refer to MK2049-34 for 3.3 V
Block Diagram
VDD
4
GND
3
RESET
FS3:0 4
Clock
Input
Reference
Crystal X1
External/
Loop Timing
Mux
Crystal
Oscillator
PLL
Clock
Synthesis,
Control, and
Jitter
Attenuation
Circuitry
X2
CAP1
CAP2
Output
Buffer
Output
Buffer
Output
Buffer
CLK1
CLK2
CLK3
8 kHz
(External
Mode only)
MDS 2049-02/03 B
1
Revision 040601
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel• www.icst.com
MK2049-02/03
Communications Clock PLLs
MK2049-02 Output Decoding Table – External Mode (MHz)
ICLK
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
FS3 FS2 FS1 FS0
0000
0001
0010
0011
0100
0101
0110
0111
1100
1101
CLK1
(Note 3)
1.544
2.048
22.368
17.184
19.44
16.384
24.576
25.92
10.24
4.096
CLK2 Crystal
3.088
4.096
44.736
34.368
38.88
32.768
49.152
51.84
20.48
8.192
12.352
12.288
11.184
11.456
12.96
8.192
12.288
12.96
10.24
12.288
CLK3
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
MK2049-02 Output Decoding Table – Loop Timing Mode (MHz)
ICLK
1.544
2.048
44.736
34.368
FS3 FS2 FS1 FS0
1000
1001
1010
1011
CLK1
(Note 3)
1.544
2.048
22.368
17.184
CLK2 Crystal
3.088
4.096
44.736
34.368
12.352
12.288
11.184
11.456
CLK3
N/A
N/A
N/A
N/A
MK2049-02 Output Decoding Table – Buffer Mode (MHz)
ICLK
19 - 28
10 - 14
FS3 FS2 FS1 FS0
1110
1111
CLK1
(Note 3)
ICLK/2
2*ICLK
CLK2 Crystal
ICLK ICLK/2
4*ICLK ICLK
• 0 = connect directly to ground, 1 = connect directly to VDD.
• Crystal is connected to pins 2 and 3; clock input is applied to pin 13.
CLK3
N/A
N/A
= No Zero (Fixed) I/O Delay for these selections shown in the shaded boxes.
Note 3: CLK1 rising or falling edge may align with the input clock. See Figure 1 on page 6
for more details.
MDS 2049-02/03 B
4
Revision 040601
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel• www.icst.com
4페이지 MK2049-02/03
Communications Clock PLLs
INPUT AND OUTPUT SYNCHRONIZATION (continued)
MK2049-03
As illustrated in the diagram below, when using the MK2049-03 in one of the Zero Delay selections, the
rising edge of ICLK will be aligned with the rising edges of CLK1 and CLK2.
ICLK (8 kHz)
CLK2 (MHz)
CLK1 (MHz)
Figure 2. MK2049-03 Input and Output Clock Waveforms in Zero Delay Selections
In the MK2049-02 and MK2049-03 selections that are not Zero Delay, the phase relationship between the
input and output clocks is not predictable. Although it will not change once the MK2049-02/03 is running,
this relationship is likely to change when power is interrupted.
Measuring Zero Delay on the MK2049
The MK2049-02/03 both produce low-jitter output clocks. In addition, both parts have a very low
bandwidth--on the order of a few Hertz. Since most 8 kHz input clocks will have high jitter, this can make
measuring the input-to-output skew (zero delay feature) very difficult. The MK2049 are designed to reject
the input jitter; when the input and output clocks are both displayed on an oscilloscope, they may appear
not to be locked because the scope trigger point is constantly changing with the input jitter. In fact, the
input and output clocks probably are locked, and the MK2049 will have zero delay to the average position
of the 8 kHz input clock. In order to see this clearly, a low jitter 8 kHz input clock is necessary. Most lab
frequency sources are NOT SUITABLE for this since they have high jitter at low frequencies.
Frequency Locking to the Input
In all modes, the output clocks are frequency-locked to the input. The output will remain at the specified
output frequency as long as the combined variation of the input frequency and the crystal does not exceed
100 ppm. For example, if the crystal can vary ±40 ppm (initial accuracy + temperature + aging), then the
input frequency can vary by up to 60 ppm and still have the output clock remain frequency-locked.
MDS 2049-02/03 B
7
Revision 040601
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel• www.icst.com
7페이지 | |||
구 성 | 총 12 페이지수 | ||
다운로드 | [ MK2049-02.PDF 데이터시트 ] |
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부품번호 | 상세설명 및 기능 | 제조사 |
MK2049-01 | Communications Clock PLL | Integrated Circuit Systems |
MK2049-02 | Communications Clock PLLs | Integrated Circuit Systems |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |