|
|
PDF MK2049-36 Data sheet ( Hoja de datos )
| Número de pieza | MK2049-36 | |
| Descripción | 3.3 V Communications Clock PLL | |
| Fabricantes | Integrated Circuit Systems | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de MK2049-36 (archivo pdf) en la parte inferior de esta página. Total 10 Páginas | ||
|
No Preview Available !
PRELIMINARY INFORMATION
MK2049-36
3.3 V Communications Clock PLL
Description
The MK2049-36 is a Phase-Locked Loop (PLL)
based clock synthesizer that accepts multiple input
frequencies. With an 8 kHz clock input as a
reference, the MK2049-36 generates T1, E1, T3,
E3, OC3/3, Gigabit Ethernet, and other
communications frequencies. This allows for the
generation of clocks frequency-locked to an 8 kHz
backplane clock, simplifying clock synchronization
in communications systems.
This part also has a jitter-attenuated Buffer
capability. In this mode, the MK2049-36 is ideal
for filtering jitter from with high jitter clocks.
ICS can customize these devices for many other
different frequencies. Contact your ICS
representative for more details.
Features
• Packaged in 20 pin SOIC
• 3.3 V ±5% operation
• Meets the TR62411, ETS300 011, and GR-1244
specification for MTIE, Pull-in/Hold-in Range,
Phase Transients, and Jitter Generation for
Stratum 3, 4, and 4E
• Accepts multiple inputs: 8 kHz backplane clock,
or 10 to 50 MHz
• Locks to 8 kHz ±100 ppm (External mode)
• Buffer Mode allows jitter attenuation of
10-50 MHz input and x1/x0.5 or x1/x2 outputs
• Exact internal ratios enable zero ppm error
• Output clock rates include T1, E1, T3, E3,
and OC3 submultiples
• See the MK2049-01, -02, and -03 for more
selections at VDD = 5 V, and the MK2049-34 for
more selections at 3.3 V
Block Diagram
VDD
3
GND
3
RES
FS3:0 4
Clock
Input
Reference
Crystal X1
External/
Buffer Mode
Mux
Crystal
Oscillator
X2
FCAP
PLL
Clock
Synthesis,
Control, and
Jitter
Attenuation
Circuitry
Output
Buffer
Output
Buffer
Output
Buffer
CAP1
CAP2
CLK
CLK/2
8 kHz
(External
Mode only)
MDS 2049-36 A
1
Revision 120400
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel• www.icst.com
1 page  
PRELIMINARY INFORMATION
MK2049-36
3.3 V Communications Clock PLL
OPERATING MODES
The MK2049-36 has two operating modes: External and Buffer. Although both modes use an input clock
to generate various output clocks, there are important differences in their input and crystal requirements.
External Mode
The MK2049-36 accepts an external 8 kHz clock and will produce a number of common communication
clock frequencies. The 8 kHz input clock does not need to have a 50% duty cycle; a “high” or “on” pulse
as narrow as 10 ns is acceptable.
Buffer Mode
Unlike the other mode that accepts only a single specified input frequency, Buffer Mode will accept a wider
range of input clocks. The input jitter is attenuated, and the outputs on CLK and CLK/2 also provide the
option of getting x1, x2, x4, or 1/2 of the input frequency. For example, this mode can be used to remove
the jitter from a 27 MHz clock, generating low-jitter 27 MHz and 13.5 MHz outputs.
FREQUENCY LOCKING TO THE INPUT
In all modes, the output clocks are frequency-locked to the input. The output will remain at the specified
output frequency as long as the combined variation of the input frequency and the crystal does not exceed
100 ppm. For example, if the crystal can vary ±40 ppm (initial accuracy + temperature + aging), then the
input frequency can vary by up to 60 ppm and still have the output clock remain frequency-locked.
MDS 2049-36 A
5
Revision 120400
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel• www.icst.com
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet MK2049-36.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| MK2049-34 | 3.3 V Communications Clock PLL | Integrated Circuit Systems |
| MK2049-34A | 3.3 Volt Communications Clock VCXO PLL | Integrated Circuit Systems |
| MK2049-35 | 3.3 V Communications Clock PLL | Integrated Circuit Systems |
| MK2049-36 | 3.3 V Communications Clock PLL | Integrated Circuit Systems |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |