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80C652 데이터시트 PDF




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부품번호 80C652 기능
기능 CMOS single-chip 8-bit microcontrollers
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80C652 데이터시트, 핀배열, 회로
INTEGRATED CIRCUITS
80C652/83C652
CMOS single-chip 8-bit microcontrollers
Product specification
IC20 Data Handbook
1996 Aug 15
Philips
Semiconductors




80C652 pdf, 반도체, 판매, 대치품
Phlips Semiconductors
CMOS single-chip 8-bit microcontrollers
Product specification
80C652/83C652
ORDER INFORMATION
PHILIPS
PART ORDER NUMBER
PART MARKING
ROMless
ROM3
Drawing
Number
P80C652FBP P83C652FBP/xxx SOT129-1
PHILIPS NORTH AMERICA
PART ORDER NUMBER
ROMless
ROM
P80C652FBPN P83C652FBPN
TEMPERATURE
RANGE (°C)
AND PACKAGE
0 to +70, Plastic Dual In-line Package
FREQ
MHz1,2
16
P80C652FBA P83C652FBA/xxx SOT187-2 P80C652FBAA P83C652FBAA 0 to +70, Plastic Leaded Chip Carrier
16
P80C652FBB P83C652FBB/xxx SOT307-2 4 P80C652FBBB
P80C652FFP P83C652FFP/xxx SOT129-1 P80C652FFPN
P83C652FBBB
P83C652FFPN
0 to +70, Plastic Quad Flat Pack
–40 to +85, Plastic Dual In-line Package
16
16
P80C652FFA
P80C652FFB
P80C652FHP
P80C652FHA
P80C652FHB
P83C652FFA/xxx SOT187-2 P80C652FFAA
P83C652FFB/xxx SOT307-2 4 P80C652FFBB
P83C652FHP/xxx SOT129-1 P80C652FHPN
P83C652FHA/xxx SOT187-2 P80C652FHAA
P83C652FHB/xxx SOT307-2 4 P80C652FHBB
P83C652FFAA
P83C652FFBB
P83C652FHPN
P83C652FHAA
P83C652FHBB
–40 to +85, Plastic Leaded Chip Carrier
–40 to +85, Plastic Quad Flat Pack
–40 to +125, Plastic Dual In-line Package
–40 to +125, Plastic Leaded Chip Carrier
–40 to +125, Plastic Quad Flat Pack
16
16
16
16
16
P80C652IBP P83C652IBP/xxx SOT129-1 P80C652IBPN P83C652IBPN
P80C652IBA
P80C652IBB
P83C652IBA/xxx
P83C652IBB/xxx
SOT187-2 P80C652IBAA
SOT307-2 4 P80C652IBBB
P83C652IBAA
P83C652IBBB
P80C652IFP P83C652IFP/xxx SOT129-1 P80C652IFPN P83C652IFPN
P80C652IFA P83C652IFA/xxx SOT187-2 P80C652IFAA P83C652IFAA
P80C652IFB P83C652IFB/xxx SOT307-2 4 P80C652IFBB P83C652IFBB
NOTES:
1. 80C652 and 83C652 frequency range is 1.2MHz–16MHz or 1.2 to 24MHz.
2. For specification of the EPROM version, see the 87C652 data sheet.
3. xxx denotes the ROM code number.
4. SOT311 replaced by SOT307-2.
0 to +70, Plastic Dual In-line Package
0 to +70, Plastic Leaded Chip Carrier
0 to +70, Plastic Quad Flat Pack
–40 to +85, Plastic Dual In-line Package
–40 to +85, Plastic Leaded Chip Carrier
–40 to +85, Plastic Quad Flat Pack
24
24
24
24
24
24
1996 Aug 15
4

4페이지










80C652 전자부품, 판매, 대치품
Phlips Semiconductors
CMOS single-chip 8-bit microcontrollers
Product specification
80C652/83C652
PIN DESCRIPTIONS
PIN NUMBER
MNEMONIC DIP PLCC QFP TYPE NAME AND FUNCTION
VSS 20 22 6, 16, I Ground: 0V reference. With the QFP package all VSS pins (VSS1 to VSS4) must be
28, 39
connected.
VDD
40 44
38
I Power Supply: This is the power supply voltage for normal, idle, and power-down
operation.
P0.0–0.7
39–32 43–36 37–30 I/O Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to
them float and can be used as high-impedance inputs. Port 0 is also the multiplexed
low-order address and data bus during accesses to external program and data memory. In
this application, it uses strong internal pull-ups when emitting 1s.
P1.0–P1.7
P1.6
P1.7
1–8 2–9 40–44, I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups, except P1.6 and P1.7
1–3 which are open drain. Port 1 pins that have 1s written to them are pulled high by the
internal pull-ups and can be used as inputs. As inputs, port 1 pins that are externally pulled
low will source current because of the internal pull-ups. (See DC Electrical Characteristics:
78
IIL). Alternate functions include:
2 I/O
SCL: I2C-bus serial port clock line.
89
3 I/O
SDA: I2C-bus serial port data line.
P2.0–P2.7 21–28 24–31 18–25 I/O Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s
written to them are pulled high by the internal pull-ups and can be used as inputs. As
inputs, port 2 pins that are externally being pulled low will source current because of the
internal pull-ups. (See DC Electrical Characteristics: IIL). Port 2 emits the high-order
address byte during fetches from external program memory and during accesses to
external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it
uses strong internal pull-ups when emitting 1s. During accesses to external data memory
that use 8-bit addresses (MOV @Ri), port 2 emits the contents of the P2 special function
register.
P3.0–P3.7 10–17 11,
5,
13–19 7–13
10 11
11 13
12 14
13 15
14 16
15 17
16 18
17 19
5
7
8
9
10
11
12
13
I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s
written to them are pulled high by the internal pull-ups and can be used as inputs. As
inputs, port 3 pins that are externally being pulled low will source current because of the
pull-ups. (See DC Electrical Characteristics: IIL). Port 3 also serves the special features of
the 80C51 family, as listed below:
I RxD (P3.0): Serial input port
O TxD (P3.1): Serial output port
I INT0 (P3.2): External interrupt
I INT1 (P3.3): External interrupt
I T0 (P3.4): Timer 0 external input
I T1 (P3.5): Timer 1 external input
O WR (P3.6): External data memory write strobe
O RD (P3.7): External data memory read strobe
RST
ALE
9 10
4
I Reset: A high on this pin for two machine cycles while the oscillator is running, resets the
device. An internal diffused resistor to VSS permits a power-on reset using only an external
capacitor to VDD.
30 33 27 I/O Address Latch Enable: Output pulse for latching the low byte of the address during an
access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6
the oscillator frequency. Note that one ALE pulse is skipped during each access to external
data memory.
PSEN
29 32
26
O Program Store Enable: Read strobe to external program memory via Port 0 and Port 2. It
is activated twice each machine cycle during fetches from the external program memory.
When executing out of external program memory two activations of PSEN are skipped
during each access to external data memory. PSEN is not activated (remains HIGH) during
no fetches from external program memory. PSEN can sink/source 8 LSTTL inputs and can
drive CMOS inputs without external pull–ups.
EA
31 35
29
I External Access: If during a RESET, EA is held at TTL, level HIGH, the CPU executes out
of the internal program memory ROM provided the Program Counter is less than 8192. If
during a RESET, EA is held a TTL LOW level, the CPU executes out of external program
memory. EA is not allowed to float.
XTAL1
19 21
15
I Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator
circuits.
XTAL2
18 20
14
O Crystal 2: Output from the inverting oscillator amplifier.
NOTE:
To avoid “latch-up” effect at power-on, the voltage on any pin at any time must not be higher than VDD + 0.5V or VSS – 0.5V, respectively.
1996 Aug 15
7

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80C652

CMOS single-chip 8-bit microcontrollers

NXP Semiconductors
NXP Semiconductors
80C652

CMOS single-chip 8-bit microcontrollers

NXP Semiconductors
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