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PDF MK41T56N00TR Data sheet ( Hoja de datos )
| Número de pieza | MK41T56N00TR | |
| Descripción | 512 bit 64b x8 Serial Access TIMEKEEPER SRAM | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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MK41T56
MKI41T56
512 bit (64b x8) Serial Access TIMEKEEPER® SRAM
COUNTERS for SECONDS, MINUTES,
HOURS, DAY, DATE, MONTH and YEARS
SOFTWARE CLOCK CALIBRATION
AUTOMATIC POWER-FAIL DETECT and
SWITCH CIRCUITRY
I2C BUS COMPATIBLE
56 BYTES of GENERAL PURPOSE RAM
ULTRA-LOW BATTERY SUPPLY CURRENT of
500nA
OPERATING TEMPERATURE:
– MK41T56: 0 to 70°C
– MKI41T56: –40 to 85°C
AUTOMATIC LEAP YEAR COMPENSATION
8
1
PSDIP8 (N)
0.4mm Frame
8
1
SO8 (S)
150mil Width
DESCRIPTION
The MK41T56 TIMEKEEPER® is a low power 512
bit static CMOS RAM organized as 64 words by 8
bits. Abuilt-in 32.768 kHz oscillator (external crystal
controlled) and the first 8 bytes of the RAM are used
for the clock/calendar function and are configured
in binary coded decimal (BCD) format. Addresses
and data are transferred serially via a two-line
bi-directional bus. The built-in address register is
incremented automatically after each write or read
data byte. The MK41T56 clock has a built-in power
sense circuit which detects power failures and
automatically switches to the battery supply during
power failures. The energy needed to sustain the
RAM and clock operations can be supplied from a
small lithium button cell.
Table 1. Signal Names
OSCI
Oscillator Input
OCSO
Oscillator Output
FT/OUT
Frequency Test / Output Driver
(Open Drain)
SDA
Serial Data Address Input / Output
SCL Serial Clock
VBAT
VCC
VSS
Battery Supply Voltage
Supply Voltage
Ground
March 1999
Figure 1. Logic Diagram
VCC VBAT
OSCI
SCL
MK41T56
MKI41T56
VSS
OSCO
SDA
FT/OUT
AI02304
1/15
1 page  
Table 9. Power Down/Up Mode AC Characteristics
(TA = 0 to 70°C or –40 to 85°C)
Symbol
Parameter
tPD SCL and SDA at VIH before Power Down
tFB VPFD (min) to VSO VCC Fall Time
tRB VSO to VPFD (min) VCC Rise Time
tREC SCL and SDA at VIH after Power Up
Figure 5. Power Down/Up Mode AC Waveforms
MK41T56, MKI41T56
Min Max Unit
0 ns
300 µs
100 µs
200 µs
VCC
VPFD
VSO
SDA
SCL
tPD
IBAT
tFB tRB
DATA RETENTION TIME
tREC
AI00595
OPERATION (cont’d)
The clock continually monitors VCC for an out of
tolerance condition. Should VCC fall below VPFD,
the device terminates an access in progress and
resets the device address counter. Inputs to the
device will not be recognized at this time to prevent
erroneous data from being written to the device
from an out of tolerance system. When VCC falls
below VBAT, the device automatically switches over
to the battery and powers down into an ultra low
current mode of operation to conserve battery life.
Upon power-up, the device switches from battery
to VCC at VBAT and recognizes inputs when VCC
goes above VPFD volts.
2-WIRE BUS CHARACTERISTICS
This bus is intended for communication between
different ICs. It consists of two lines: one bi-direc-
tional for data signals (SDA) and one for clock
signals (SCL). Both the SDA and the SCL lines
must be connected to a positive supply voltage via
a pull-up resistor.
The following protocol has been defined:
– Data transfer may be initiated only when the
bus is not busy.
– During data transfer, the data line must remain
stable whenever the clock line is High.
– Changes in the data line while the clock line is
High will be interpreted as control signals.
5/15
5 Page 
Figure 14. Crystal Accuracy Across Temperature
MK41T56, MKI41T56
ppm
20
0
-20
-40
-60
∆F
F
= -0.038
ppm
C2
(T
-
T0)2
±
10%
T0 = 25 °C
-80
-100
0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 °C
AI02124
11/15
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| PDF Descargar | [ Datasheet MK41T56N00TR.PDF ] | |
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