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PDF MK74ZD133 Data sheet ( Hoja de datos )
| Número de pieza | MK74ZD133 | |
| Descripción | PLL and 32-Output Clock Driver | |
| Fabricantes | Integrated Circuit Systems | |
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PRELIMINARY INFORMATION
MK74ZD133
PLL and 32-Output Clock Driver
Description
The MK74ZD133 is a monolithic CMOS high
speed clock driver that includes an on-chip PLL
(Phase Locked Loop). Ideal for communications
and other systems that require a large number of
high-speed clocks, the unique combination of PLL
and 32 outputs can eliminate oscillators and
multiple low skew buffers. With 32 outputs
included in one device, there is also no need to
worry about chip-to-chip skew. The zero delay
modes cause the input clock rising edge to be
synchronized with all of the outputs’ rising edges.
The MK74ZD133 has a large selection of built-in
multipliers, making it possible to run from a clock
input as low as 10 MHz and generate high
frequency outputs up to 80 MHz in the SSOP. For
speeds up to 133.33 MHz, use the LQFP package.
Features
• 56 pin SSOP or 64 pin LQFP package
• On-chip PLL generates output clocks up to
80 MHz (SSOP) or 133.33 MHz (LQFP)
• Zero delay plus multiplier function
• 32 low-skew outputs can eliminate chip-to-chip
skew concerns in systems with less than 33 clocks
• Output to output skew of 200 ps (with stagger)
• Device to device skew of 700ps
• Staggered, fixed skew helps reduce EMI
• Tri-state (Output Enable) pin
• Output blocks can be independently powered off
• 250 ps typical fixed delay between input and
output in “Multiplier” mode
• Ideal for Fast Ethernet and Gigabit Ethernet
designs
• Good for video servers
• 3.3V±5% supply voltage
Block Diagram
Optional External Connection to Output 3 (for Zero Delay Mode)
VDD GND
FBIN
S4:0
Clock input
5
Input
Buffer
Clock
Synthesis
Circuitry
Output
Buffer
Output
Buffer
Output
Buffer
Output
Buffer
Output 1
Output 2
Output 3
Output 32
OE (all outputs)
MDS 74ZD133 C
1
Revision 010899
Printed 11/17/00
Integrated Circuit Systems, Inc.•525 Race Street•San Jose•CA•95126•(408)295-9800tel•www.icst.com
1 page  
PRELIMINARY INFORMATION
MK74ZD133
PLL and 32-Output Clock Driver
Output Frequency Select Table
Output Frequency Generation
Address S4 S3 S2 S1 S0
0 00000
1 00001
2 00010
3 00011
4 00100
5 00101
6 00110
7 00111
8 01000
9 01001
10 0 1 0 1 0
11 0 1 0 1 1
12 0 1 1 0 0
13 0 1 1 0 1
14 0 1 1 1 0
15 0 1 1 1 1
16 1 0 0 0 0
17 1 0 0 0 1
18 1 0 0 1 0
19 1 0 0 1 1
20 1 0 1 0 0
21 1 0 1 0 1
22 1 0 1 1 0
23 1 0 1 1 1
24 1 1 0 0 0
25 1 1 0 0 1
26 1 1 0 1 0
27 1 1 0 1 1
28 1 1 1 0 0
29 1 1 1 0 1
30 1 1 1 1 0
31 1 1 1 1 1
Input (F)
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
7 - 26.5
3 - 10
4 - 13.33
5 - 16
reserved
10 - 40
6 - 20
20 - 80
Input (Y)
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
7 - 44.44
3 - 16.67
4 - 22.22
5 - 26.67
reserved
10 - 66.67
6 - 33.33
20 - 100
Output
90*
30
81*
25
54
50
33.33
27
64
75
83.33*
66.66
133.33*
62.5
31.25
125*
55
53.125
135*
106.25*
106*
106.25*
106.66*
107*
x3
x8
x6
x5
reserved
x2
x4
x1
The MK74ZD133 has two primary
modes of operation: “Clock Generator”
and “Zero Delay Multiplier”.
In Clock Generator mode, addresses 0
through 23, specific output frequencies
are generated from a 20 MHz input.
There is no fixed phase relationship
between the input and output clocks.
In Zero Delay Multiplier mode,
addresses 24 through 31, the output
frequency is a simple integer multiple of
the input. The input range can vary over
several MHz, making it possible to
generate output frequencies that are not
included in Clock Generator mode. In
this mode, FBOUT3 is fed back to the
FBIN pin, and the rising edges of the
input and outputs are synchronized.
Configuring the Input/Output
Pins
The MK74ZD133 uses I/O pins whose
status as select inputs are sampled upon
power-up. The chip then selects this
address in the table to the left, and stays
in that configuration until a new power-
up sequence, when the select inputs are
sampled again. These pins all have
internal pull-up resistors, so the 10kΩ
resistor is only needed to connect to
ground for the 0 selection in the table
(as shown below).
* These modes only guaranteed in the Y (LQFP) package
For select
= 0 (low)
33Ω
I/O
to load
10kΩ
Don’t stuff 10k
for“1” selection
MDS 74ZD133 C
5
Revision 010899
Printed 11/17/00
Integrated Circuit Systems, Inc.•525 Race Street•San Jose•CA•95126•(408)295-9800tel•www.icst.com
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet MK74ZD133.PDF ] | |
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