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ML2008CP 데이터시트 PDF




Micro Linear에서 제조한 전자 부품 ML2008CP은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


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부품번호 ML2008CP 기능
기능 P Compatible Logarithmic Gain/Attenuator
제조업체 Micro Linear
로고 Micro Linear 로고


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ML2008CP 데이터시트, 핀배열, 회로
March 1997
ML2008*, ML2009**
µP Compatible Logarithmic Gain/Attenuator
GENERAL DESCRIPTION
The ML2008 and ML2009 are digitally controlled
logarithmic gain/attenuators with a range of –24 to +24dB
in 0.1dB steps.
Easy interface to microprocessors is provided by an input
latch and control signals consisting of chip select and
write.
The interface for gain setting of the ML2008 is by an 8-bit
data word, while the ML2009 is designed to interface to a
16-bit data bus with a single write operation by hard-
wiring the gain/attenuation pin or LSB pin. The ML2008
can be power downed by the microprocessor utilizing a
bit in the second write operation.
Absolute gain accuracy is 0.05dB max over supply
tolerance of ±10% and temperature range.
These CMOS logarithmic gain/attenuators are designed for
a wide variety of applications in telecom, audio, sonar or
general purpose function generation.
FEATURES
s Low noise
0dBrnc max with +24dB gain
s Low harmonic distortion
–60dB max
s Gain range
–24 to +24dB
s Resolution
0.1dB steps
s Flat frequency response
±0.05dB from 0.3-4kHz
±0.10dB from 0.1-20kHz
s Low supply current
4mA max from ±5V supplies
s TTL/CMOS compatible digital interface
s ML2008 is designed to interface to an 8-bit data bus;
ML2009 to 16-bit data bus
* This Part Is End Of Life As Of August 1, 2000
** This Part Is Obsolete
BLOCK DIAGRAM
ML2008
ML2009*
VCC VSS GND AGND
VCC VSS GND AGND
+5
VIN
WR
CS
A0
–5
+
COARSE
RESISTORS/
SWITCHES
16
+
FINE
RESISTORS/
SWITCHES
16
+
BUFFER
VOUT
DECODERS
8
REGISTER 0
1
PDN
1
REGISTER 1
8
D1–D8
+5
VIN
WR
CS
–5
+
COARSE
+
FINE
RESISTORS/
SWITCHES
16
RESISTORS/
SWITCHES
16
DECODERS
9
REGISTER 0
9
D0–D8
+
BUFFER
VOUT
1




ML2008CP pdf, 반도체, 판매, 대치품
ML2008, ML2009
ELECTRICAL CHARACTERISTICS (Continued)
SYMBOL
PARAMETER
NOTES
CONDITIONS
MIN
TYP
NOTE 3
MAX
UNITS
Digital and DC
VIL
Digital Input Low Voltage
4
VIH
Digital Input High Voltage
4
IIN Input Current, Low
4 VIH = GND
IIN Input Current, High
4 VIH = VCC
ICC VCC Supply Current
4 No output load, VIL = GND,
VIH = VCC, VIN = 0
ISS VSS Supply Current
4 No output load, VIL = GND,
VIH = VCC, VIN = 0
ICCP VCC Supply Current, ML2008 4 No output load, VIL = GND,
Powerdown Mode Only
VIH = VCC
ISSP VSS Supply Current, ML2008 4 No output load, VIL = GND,
Powerdown Mode Only
VIH = VCC
AC Characteristics
2.0
0.8 V
V
–10 µA
10 µA
4 mA
–4 mA
0.5 mA
–0.1 mA
tSET VOUT Settling Time
4 tVoIN+2=40d.B1.8M5Ve.aCsuhraenfgroemgaWinRfrroimsin–g24
edge to when VOUT settles to within
0.05dB of final value.
20 µs
tSTEP
VOUT Step Response
4 Gain = +24dB. VIN = –3V to +3V step.
Measure from VIN = –3V to when VOUT
settles to within 0.05dB of final value.
20 µs
tDS Data Setup Time
tDH Data Hold Time
tAS A0 Setup Time
tAH A0 Hold Time
tCSS CS* Setup Time
tCSH CS* Hold Time
tPW WR* Pulse Width
4
4
4
4
4
4
4
50 ns
50 ns
0 ns
0 ns
0 ns
0 ns
50 ns
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Absolute maximum ratings are limits beyond which the life of the integrated circuit may be impaired. All voltages unless otherwise specified are measured with
respect to ground.
0°C to +70°C and –40°C to +85°C operating temperature range devices are 100% tested with temperature limits guaranteed by 100% testing, sampling, or by
correlation with worst-case test conditions.
Typicals are parametric norm at 25°C.
Parameter guaranteed and 100% production tested.
Parameter guaranteed. Parameters not 100% tested are not in outgoing quality level calculation.
4

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ML2008CP 전자부품, 판매, 대치품
desired gain setting. The relationship between the register
0 and 1 bits and the corresponding analog gain values is
shown in Tables 1 and 2. Note that C3-C0 select the
coarse gain, F3-F0 select the fine gain, and ATTEN/GAIN
selects either gain or attenuation.
1.3 Output Buffer
The final analog stage is the output buffer. This amplifier
has internal gain of 1 and is designed to drive 600,
100pF loads. Thus, it is suitable for driving a telephone
hybrid circuit directly without any external amplifier.
Table 1. Fine Gain Settings (C3 – C0 = 0)
Ideal Gain (dB)
F3 F2 F1 F0 ATTEN/GAIN = 1 ATTEN/GAIN = 0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0.0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
–0.8
–0.9
–1.0
–1.1
–1.2
–1.3
–1.4
–1.5
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
2.0 DIGITAL INTERFACE
The architecture of the digital section is shown in the
preceding black diagram.
The structure of the data registers or latches is shown in
Figures 10 and 11 for the ML2008 and ML2009,
respectively. The registers control the attenuation/gain
setting bits and with the ML2008 the power down bit.
Tables 1 and 2 describe how the data word programs the
gain.
The difference between the ML2008 and ML2009 is in the
register structure. The ML2008 is an 8-bit data bus
version. This device has one 8-bit register and one 2-bit
register to store the 9 gain setting bits and 1 powerdown
bit. Two write operations are necessary to program the full
10 data bits from eight external data pins. The address pin
A0 controls which register is being written into. The
powerdown bit, PDN, causes the device to be placed in
powerdown. When PDN = 1, the device is powered
ML2008, ML2009
1.4 Power Supplies
The digital section is powered between VCC and GND,
or 5V. The analog section is powered between VCC and
VSS and uses AGND as the reference point, or ±5V.
GND and AGND are totally isolated inside the device to
minimize coupling from the digital section into the analog
section. Typically this is less than 100µV. However, AGND
and GND should be tied together physically near the
device and ideally close to the common power supply
ground connection.
Typically, the power supply rejection of VCC and VSS
to the analog output is greater than –60dB at 1KHz. If
decoupling of the power supplies is still necessary in a
system, VCC and VSS should be decoupled with respect
to AGND.
Table 2. Coarse Gain Settings (F3 – F0 = 0)
Ideal Gain (dB)
C3 C2 C1 C0 ATTEN/GAIN = 1 ATTEN/GAIN = 0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0.0
–1.5
–3.0
–4.5
–6.0
–7.5
–9.0
–10.5
–12.0
–13.5
–15.0
–16.5
–18.0
–19.5
–21.0
–22.5
0.0
1.5
3.0
4.5
6.0
7.5
9.0
10.5
12.0
13.5
15.0
16.5
18.0
19.5
21.0
22.5
down. In this state, the power consumption is reduced by
removing power from the analog section and forcing the
analog output, VOUT, to a high impedance state. While the
device is in powerdown, the digital section is still
functional and the current data word remains stored in the
registers. When PDN = 0, device is in normal operation.
The ML2009 is a 9-bit data bus version. This device has
one 9-bit register to store the 9 gain setting bits. The full 9
data bits can be programmed with one write operation
from nine external data pins.
The internal registers or latches are edge triggered. The
data is transferred from the external pins to the register
output on the rising edge of WR. The address pin, A0,
controls which register the data will be written into as
shown in Figures 1 and 2. The CS control signal selects
the device by allowing the WR signal to latch in the data
only when CS is low. When CS is high, WR is inhibited
from latching in new data into the registers.
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