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PDF ML2021 Data sheet ( Hoja de datos )
| Número de pieza | ML2021 | |
| Descripción | Telephone Line Equalizer | |
| Fabricantes | Fairchild | |
| Logotipo |  |
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ML2021
Telephone Line Equalizer
www.fairchildsemi.com
Features
• Slope, height, and bandwidth adjustable
• Optimized group delays (500 Hz to 6.4 kHz)
• On chip anti-alias filter
• Bypass mode
• Low supply current 6 mA typical from ±5V supplies
• TTL / CMOS compatible interface
• Double buffered data latch
• Selectable master clock 1.544 or 1.536 MHz
• Synchronous or asynchronous data loading capability
• Compatible with ML2003 and ML2004 logarithmic
gain/attenuator
General Description
The ML2021 is a monolithic analog line equalizer for tele-
phone applications. The ML2021 consists of a switched
capacitor filter that realizes a family of frequency response
curves optimized for telephone line equalization while mini-
mizing group delay.
The ML2021 consists of a continuous anti-aliasing filter,
three programmable switched capacitor equalization filters,
an output smoothing filter, a 600Ω driver, and a digital
section for the serial interface.
The equalization filters adjust the slope, height, and band-
width of the frequency response. The desired frequency
response is programmed by a digital 14-bit serial input data
stream.
Block Diagram
CLKSEL
CLK
CLOCK
GENERATOR
VCC AGND VSS
SMOOTHING
FILTER
VOUT
VIN
ANTIALIAS
LO PASS
MUX
PDN
LATI
SID
SLOPE
SECTION
HEIGHT BANDPASS
SECTION SECTION
5 44
14-BIT LATCH
14
14-BIT SHIFT REGISTER
1
GND
SOD
SCK
LATO
Pin Connections
ML2021
16-PIN DIP
CLKSEL 1
SID 2
NC
LATO
3
4
16 VCC
15 PDN
14 VOUT
13 AGND
SCK
NC
SOD
5
6
7
12 VIN
11 VSS
10 LATI
CLK 8
9 GND
TOP VIEW
ML2021
18-PIN SOIC
CLKSEL
SID
NC
LATO
SCK
NC
SOD
CLK
GND
1 18
2 17
3 16
4 15
5 14
6 13
7 12
8 11
9 10
TOP VIEW
VCC
PDN
VOUT
AGND
NC
VIN
NC
VSS
LATI
REV. 1.1.1 3/19/01
1 page  
PRODUCT SPECIFICATION
SCK
SID
SOD
SCK
LATI
LATO
SOD
tS
tD
tSCK
tSCK
tH
tIS tIH
tIPW
tOS tOH
tOPW
tPLD
TIMING PARAMETERS ARE REFERENCED TO THE 1.4 VOLT MIDPOINT.
Figure 1. Serial Timing Diagram
ML2021
12
10.5
9.0
7.5
6.0
4.5
3.0
1.5
0
–1.5
–3.0
0
1111
0000
500 1000 1500 2000 2500 3000 3500 4000
FREQUENCY (Hz)
120
100
80
60
40
20
0
–20
–40
–60
–80
0
0100 1000
1111
0001 0010
0000
500 1000 1500 2000 2500 3000 3500 4000
FREQUENCY (Hz)
Figure 2. Typical Slope Filter Response—NL/L = 0
B3-B0, H3-H0 = 0000, S3-S0 = 0000 to 1111.
REV. 1.1.1 3/19/01
5
5 Page 
ML2021
Ordering Information
Part Number
ML2021CP
ML2021CS
ML2021IP
ML2021IS
Temperature Range
0°C to 70°C
0°C to 70°C
-40°C to 85°C
-40°C to 85°C
PRODUCT SPECIFICATION
Package
Molded DIP (P16)
Molded SOIC (S18)
Molded DIP (P16)
Molded SOIC (S18)
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO
ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME
ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
3/19/01 0.0m 003
Stock#DS300042021
2001 Fairchild Semiconductor Corporation
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet ML2021.PDF ] | |
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