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ML2035 데이터시트 PDF




Micro Linear에서 제조한 전자 부품 ML2035은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 ML2035 자료 제공

부품번호 ML2035 기능
기능 Serial Input Programmable Sine Wave Generator
제조업체 Micro Linear
로고 Micro Linear 로고


ML2035 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.




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ML2035 데이터시트, 핀배열, 회로
February 1997
ML2035
Serial Input Programmable Sine Wave Generator
GENERAL DESCRIPTION
The ML2035 is a monolithic sinewave generator whose
output is programmable from DC to 25kHz. No external
components are required. The frequency of the sinewave
output is derived from either an external crystal or clock
input, providing a stable and accurate frequency
reference. The frequency is programmed by a 16-bit serial
data word. The ML2035 has a VOUT amplitude of ±VCC/2.
The ML2035 is intended for telecommunications and
modem applications that need low cost and accurate
generation of precise test tones, call progress tones, and
signaling tones.
FEATURES
s Programmable output frequency - DC to 25kHz
s Low gain error and total harmonic distortion
s 3-wire SPI compatible serial microprocessor interface
with double buffered data latch
s Fully integrated solution - no external components
required
s Frequency resolution of 1.5Hz (±0.75Hz) with a
12MHz clock input
s Onboard 3 to 12MHz crystal oscillator
s Synchronous or asynchronous data loading capability
s Compatible with ML2031 and ML2032 tone detectors
and ML2004 logarithmic gain/attenuator
BLOCK DIAGRAM
5k
CLK IN
8
CRYSTAL
OSCILLATOR
LATI
4
÷4
8-BIT
DAC
8
PHASE
ACCUMULATOR
& 512 POINT
SINE LOOK-UP
TABLE
16
16-BIT DATA LATCH
SCK
2
SID
3
16
16-BIT SHIFT REGISTER
SMOOTHING
FILTER
5k
-
+
VOUT
6
ZERO
DETECT
VCC
5
GND
7
VSS
1
1




ML2035 pdf, 반도체, 판매, 대치품
ML2035
ELECTRICAL CHARACTERISTICS (Continued)
SYMBOL
PARAMETER
CONDITIONS
MIN TYP MAX UNITS
LOGIC (Continued)
VOL Output Low Voltage
IOL = -2mA
0.4 V
VOH
tSCK
tDS
tDH
tLPW
Output High Voltage
Serial Clock On/Off Period
SID Data Setup Time
SID Data Hold Time
LATI Pulse Width
IOH = 2mA
4.0 V
100 ns
50 ns
50 ns
50 ns
tLH
tLS
SUPPLY
LATI Hold Time
LATI Setup Time
50 ns
50 ns
ICC VCC Current
No Load, VCC = 5.5V
No Load, Power Down Mode
5.5 mA
2 mA
ISS VSS Current
No Load, VCC = 5.5V, VSS = -5.5V
No Load, Power Down Mode
-3.5
-100
mA
µA
Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst case test conditions.
CLK IN
SCK
SID
LATI
tCKI tCKI
tSCK tSCK
tDS tDH
tLH
tLS
tLPW
Figure 1. Serial Interface Timing.
100
75
50
25
0
-25
-50
-75
-100
0
1234
INPUT VOLTAGE (V)
5
Figure 2. CLK IN Input Current vs. Input Voltage.
4

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ML2035 전자부품, 판매, 대치품
ML2035
SCK
SID
LATI
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Figure 4. Serial Interface Timing.
FUNCTIONAL DESCRIPTION (Continued)
SERIAL DIGITAL INTERFACE
The digital interface consists of a shift register and data
latch. The serial 16-bit data word on SID is clocked into a
16-bit shift register on rising edges of the serial shift clock,
SCK. The LSB should be shifted in first and the MSB last as
shown in Figure 4. The data that has been shifted into the
shift register is loaded into a 16-bit data latch on the falling
edge of LATI. To insure that true data is loaded into the
data latch from the shift register, LATI falling edge should
occur when SCK is low, as shown in figure 1. LATI should
be low while shifting data into the shift register to avoid
inadvertently entering the power down mode. Note that all
data is entered and latched on the edges, not levels, of
SCK and LATI.
POWER DOWN MODE
The power down mode of the ML2035 can be selected by
entering all zeros in the shift register and applying a logic
“1” to LATI and holding it high. A zero data detect circuit
detects when all bits in the shift register are zeros. In this
state, the power consumption is reduced to 11.5mW max,
and VOUT goes to 0V as shown in Figure 5 and appears as
10kW to ground. The master clock, CLK IN, can be left
active or removed during power down mode.
POWER SUPPLIES
The analog circuits in ML2035 are powered from VCC to
VSS and are referenced to GND. The digital circuits in the
device are powered from VCC to GND.
It is recommended that the power supplies to the device
should be bypassed by placing decoupling capacitors from
VCC to GND and VSS to GND as physically close to the
device as possible.
POWER DOWN MODE
VOS
0V
SCK
SID
LATI
0 1 2 3 4 5 6 7 8 9 10 11 12 131415
Figure 5. Power Down Mode Waveforms.
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일반 IC 문의 : 샘플 및 소량 구매
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