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PDF ML2036 Data sheet ( Hoja de datos )
| Número de pieza | ML2036 | |
| Descripción | Serial Input Programmable Sine Wave Generator with Digital Gain Control | |
| Fabricantes | Fairchild | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ML2036 (archivo pdf) en la parte inferior de esta página. Total 12 Páginas | ||
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www.fairchildsemi.com
ML2036
Serial Input Programmable Sine Wave Generator
with Digital Gain Control
Features
• Programmable output frequency – DC to 50kHz
• Low gain error and total harmonic distortion
• 3-wire SPI compatible serial microprocessor interface
with double buffered data latch
• Fully integrated solution – no external components
required
• Frequency resolution of 1.5Hz (±0.75Hz) with a 12MHz
clock input
• Onboard 3 to 12MHz crystal oscillator
• Clock outputs of 1/2 or 1/8 of the input clock frequency
• Synchronous or asynchronous data loading capability
• Compatible with ML2004 logarithmic gain/attenuator
General Description
The ML2036 is a monolithic sine wave generator whose
output is programmable from DC to 50kHz. No external
components are required. The frequency of the sinewave
output is derived from either an external crystal or clock
input, providing a stable and accurate frequency reference.
The frequency is programmed by a 16-bit serial data word.
The ML2036 provides for a VOUT amplitude of either ±VREF
or ±VREF/2. Also included with the ML2036 is an inhibit
function which allows the sinewave output to be held at zero
volts after completing the last half cycle of the sine wave in
progress. Two digital clock outputs are provided to drive
other devices with one half or one eighth of the input clock
frequency.
The ML2036 is intended for telecommunications and
modem applications that need low cost and accurate genera-
tion of precise test tones, call progress tones, and signaling
tones.
Block Diagram (Pin configuration shown for 14-Pin PDIP Version)
9
VREF
13
GAIN
5kΩ
5kΩ
CLK IN
14
CRYSTAL
OSCILLATOR
8-BIT
DAC
CLK OUT 1
3 ÷2
÷2
CLK OUT 2
4 ÷2
LATI
7
8
PHASE
ACCUMULATOR
& 512 POINT
SINE LOOK-UP
TABLE
16
16-BIT DATA LATCH
SMOOTHING
FILTER
SCK
5
SID
3
16
16-BIT SHIFT REGISTER
- VOUT
+ 10
VCC
8
ZERO
DETECT
AGND
11
DGND
12
VSS
1
PDN-INH
2
REV. 1.0.2 7/26/01
1 page  
PRODUCT SPECIFICATION
CLKIN
CLKOUT1
CLKOUT2
CLK IN
SCK
SID
LATI
tCKI tCKI
tSCK tSCK
tDS tDH
tLH
tLS
tLPW
Figure 1. Serial Interface Timing.
fCLKIN
fCLK1
fCLK2
t2F
t1R
t1F
fCLK PARAMETERS REFERRED TO 1.4V MIDPOINT
Figure 2. Digital Clock Output Timing
100
75
50
25
0
-25
-50
-75
-100
0
1234
INPUT VOLTAGE (V)
5
Figure 3. CLK IN Input Current vs. Input Voltage.
ML2036
t2R
REV. 1.0.2 7/26/01
5
5 Page 
PRODUCT SPECIFICATION
Mechanical Dimensions Inches (Millimeters)
Package: P14
14-Pin PDIP
0.740 - 0.760
(18.79 - 19.31)
14
PIN 1 ID
0.240 - 0.260 0.295 - 0.325
(6.09 - 6.61) (7.49 - 8.25)
0.070 MIN
(1.77 MIN)
(4 PLACES)
1
0.050 - 0.065 0.100 BSC
(1.27 - 1.65) (2.54 BSC)
0.170 MAX
(4.32 MAX)
0.015 MIN
(0.38 MIN)
0.125 MIN
(3.18 MIN)
0.016 - 0.022 SEATING PLANE
(0.40 - 0.56)
0º - 15º
0.008 - 0.012
(0.20 - 0.31)
ML2036
0.400 - 0.414
(10.16 - 10.52)
16
Package: S16W
16-Pin Wide SOIC
PIN 1 ID
0.291 - 0.301 0.398 - 0.412
(7.39 - 7.65) (10.11 - 10.47)
0.024 - 0.034
(0.61 - 0.86)
(4 PLACES)
1
0.050 BSC
(1.27 BSC)
0.095 - 0.107
(2.41 - 2.72)
0º - 8º
0.090 - 0.094
(2.28 - 2.39)
0.012 - 0.020
(0.30 - 0.51)
SEATING PLANE 0.005 - 0.013
(0.13 - 0.33)
0.022 - 0.042
(0.56 - 1.07)
0.009 - 0.013
(0.22 - 0.33)
REV. 1.0.2 7/26/01
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet ML2036.PDF ] | |
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