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PDF ML4841 Data sheet ( Hoja de datos )
| Número de pieza | ML4841 | |
| Descripción | Variable Feedforward PFC/PWM Controller Combo | |
| Fabricantes | Fairchild | |
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www.fairchildsemi.com
ML4841
Variable Feedforward PFC/PWM Controller Combo
Features
• Internally synchronized PFC and PWM in one IC
• Low total harmonic distortion
• Reduces ripple current in the storage capacitor between
the PFC and PWM sections
• Average current, continuous mode, boost type, leading
edge PFC
• High efficiency trailing edge PWM can be configured for
current mode or voltage mode operation
• Average line voltage compensation with brown-out
control
• PFC overvoltage comparator eliminates output
“runaway” due to load removal
• Current fed multiplier for improved noise immunity
• Overvoltage protection, UVLO, and soft start
General Description
The ML4841 is a controller for power factor corrected,
switched mode power supplies. Power Factor Correction
(PFC) allows the use of smaller, lower cost bulk capacitors,
reduces power line loading and stress on the switching FETs,
and results in a power supply that fully complies with
IEC1000-2-3 specifications. The ML4841 includes circuits
for the implementation of a leading edge, average current,
“boost” type power factor correction, and a trailing edge,
pulse width modulator (PWM).
The PFC frequency of the ML4841 is automatically set at
half that of the PWM frequency generated by the internal
oscillator. This technique allows the user to design with
smaller output components while maintaining the optimum
operating frequency for the PFC. An over-voltage compara-
tor shuts down the PFC section in the event of a sudden
decrease in load. The PFC section also includes peak current
limiting and input voltage brown-out protection.
Block Diagram
16
VEAO
1
IEAO
POWER FACTOR CORRECTOR
VFB
15
2.5V
IAC
2
VRMS
4
ISENSE
3
VEA
-
+
3.5kΩ IEA
-
+
GAIN
MODULATOR
8V
3.5kΩ
RAMP 1
8
RTCT
7
+
-
OSCILLATOR
÷2
2.7V
OVP
+
-
-1V +
-
PFC ILIMIT
VCCZ
13.5V
13
VCC
7.5V
REFERENCE
VREF
14
SQ
RQ
SQ
PFC OUT
12
RQ
RAMP 2
9
8V
VDC
6
VCC
1.25V
SS
5
50µA
8V
-
+
-
+
DUTY CYCLE
LIMIT
VFB
VIN OK
-
+
2.5V +
1V -
DC ILIMIT
SQ
RQ
PWM OUT
11
PULSE WIDTH MODULATOR
VCCZ
UVLO
REV. 1.0.3 6/13/01
1 page  
PRODUCT SPECIFICATION
ML4841
Electrical Characteristics (continued)
Unless otherwise specified, ICC = 25mA, RT = 23kΩ, RRAMP1 = 28.7kΩ, CT = 400pF, CRAMP1 = 270pF, TA =
Operating Temperature Range (Note 1)
Symbol
Reference
Parameter
Conditions
Min. Typ. Max. Units
Output Voltage
Line Regulation
Load Regulation
Temperature Stability
Total Variation
TA = 25°C, I(VREF) = 1mA
VCCZ - 3V < VCC < VCCZ - 0.5V
1mA < I(VREF) < 20mA
Line, Load, Temp
7.4 7.5 7.6 V
2 10 mV
2 15 mV
0.4 %
7.25 7.65 V
PFC
Long Term Stability
TJ = 125°C, 1000 Hours
5 25 mV
Minimum Duty Cycle
Maximum Duty Cycle
Output Low Voltage
Output High Voltage
PWM
DC
Rise/Fall Time
Duty Cycle Range
VIEAO > 6.7V
VIEAO < 1.2V
IOUT = -20mA
IOUT = -100mA
IOUT = 10mA, VCC = 8V
IOUT = 20mA
IOUT = 100mA
CL = 1000pF
0
90 95
0.4 0.8
0.7 2.0
0.8 1.5
10 10.5
9.5 10
50
%
%
V
V
V
V
V
ns
0-44 0-47 0-50 %
VOL Output Low Voltage
VOH Output High Voltage
Rise/Fall Time
Supply
IOUT = -20mA
IOUT = -100mA
IOUT = 10mA, VCC = 8V
IOUT = 20mA
IOUT = 100mA
CL = 1000pF
0.4 0.8
0.7 2.0
0.8 1.5
10 10.5
9.5 10
50
V
V
V
V
V
ns
VCCZ
Shunt Regulator Voltage
VCCZ Load Regulation
VCCZ Total Variation
Start-up Current
Operating Current
Undervoltage Lockout
Threshold
Undervoltage Lockout
Hysteresis
25mA < ICC < 55mA
Load, Temp
VCC = 11.2V, CL = 0
VCC < VCCZ - 0.5V, CL = 0
12.8 13.5 14.2
±100 ±200
12.4 14.6
0.7 1.0
17 21
VCCZ - VCCZ - VCCZ -
1.0 0.7 0.4
2.7 3.0 3.3
V
mV
V
mA
mA
V
V
Notes
1. Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.
2. Includes all bias currents to other circuits connected to the VFB pin.
3. Gain = K x 5.3V; K = (IGAINMOD - IOFFSET) x IAC x (VEAO - 1.5V)-1.
REV. 1.0.3 6/13/01
5
5 Page 
PRODUCT SPECIFICATION
ML4841
The ML4841 should be locally bypassed with a 10nF and a
1µF ceramic capacitor. In most applications, an electrolytic
capacitor of between 100µF and 330µF is also required
across the part, both for filtering and as part of the start-up
bootstrap circuitry.
Leading/Trailing Modulation
Conventional Pulse Width Modulation (PWM) techniques
employ trailing edge modulation in which the switch will
turn on right after the trailing edge of the system clock.
The error amplifier output voltage is then compared with the
modulating ramp. When the modulating ramp reaches the
level of the error amplifier output voltage, the switch will be
turned OFF. When the switch is ON, the inductor current will
ramp up. The effective duty cycle of the trailing edge modu-
lation is determined during the ON time of the switch. Figure
4 shows a typical trailing edge control scheme.
In the case of leading edge modulation, the switch is turned
OFF right at the leading edge of the system clock. When the
modulating ramp reaches the level of the error amplifier
output voltage, the switch will be turned ON. The effective
duty-cycle of the leading edge modulation is determined
during the OFF time of the switch. Figure 5 shows a leading
edge control scheme.
One of the advantages of this control teccnique is that it
requires only one system clock. Switch 1 (SW1) turns off
and switch 2 (SW2) turns on at the same instant to minimize
the momentary “no-load” period, thus lowering ripple volt-
age generated by the switching action. With such synchro-
nized switching, the ripple voltage of the first stage is
reduced. Calculation and evaluation have shown that the
120Hz component of the PFC’s output ripple voltage can be
reduced by as much as 30% using this method.
L1
I1
+
VIN
DC
SW2 I2 I3
I4
SW1
C1
RL
REF +–EAU3
RAMP
OSC
CLK
U4
+
– U1
DFF
RQ
D U2
Q
CLK
RAMP
VEAO
VSW1
TIME
TIME
Figure 4. Typical Trailing Edge Control Scheme
REV. 1.0.3 6/13/01
11
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet ML4841.PDF ] | |
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