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82371SB 데이터시트 PDF




Intel Corporation에서 제조한 전자 부품 82371SB은 전자 산업 및 응용 분야에서
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부품번호 82371SB 기능
기능 82371FB (PIIX) AND 82371SB (PIIX3) PCI ISA IDE XCELERATOR
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82371SB 데이터시트, 핀배열, 회로
E
82371FB (PIIX) AND 82371SB (PIIX3)
PCI ISA IDE XCELERATOR
n Bridge Between the PCI Bus and ISA Bus
n PCI and ISA Master/Slave Interface
PCI from 25–33 MHz
ISA from 7.5–8.33 MHz
5 ISA Slots
n Fast IDE Interface
Supports PIO and Bus Master IDE
Supports up to Mode 4 Timings
Transfer Rates to 22 MB/Sec
8 x 32-Bit Buffer for Bus Master IDE PCI
Burst Transfers
Separate Master/Slave IDE Mode
Support (PIIX3)
n Plug-n-Play Port for Motherboard Devices
2 Steerable DMA Channels (PIIX Only)
Fast DMA with 4-Byte Buffer (PIIX Only)
2 Steerable Interrupts Lines on the PIIX
and 1 Steerable Interrupt Line on the
PIIX3
1 Programmable Chip Select
n Steerable PCI Interrupts for PCI Device Plug-
n-Play
n PCI Specification Revision 2.1 Compliant
(PIIX3)
n Functionality of One 82C54 Timer
System Timer; Refresh Request;
Speaker Tone Output
n Two 82C59 Interrupt Controller Functions
14 Interrupts Supported
Independently Programmable for
Edge/Level Sensitivity
n Enhanced DMA Functions
Two 8237 DMA Controllers
Fast Type F DMA
Compatible DMA Transfers
7 Independently Programmable
Channels
n X-Bus Peripheral Support
Chip Select Decode
Controls Lower X-Bus Data Byte
Transceiver
n I/O Advanced Programmable Interrupt
Controller (IOAPIC) Support (PIIX3)
n Universal Serial Bus (USB) Host Controller
(PIIX3)
Compatible with Universal Host
Controller Interface (UHCI)
Contains Root Hub with 2 USB Ports
n System Power Management (Intel SMM
Support)
Programmable System Management
Interrupt (SMI)—Hardware Events,
Software Events, EXTSMI#
Programmable CPU Clock Control
(STPCLK#)
Fast On/Off Mode
n Non-Maskable Interrupts (NMI)
PCI System Error Reporting
n NAND Tree for Board-Level ATE Testing
n 208-Pin QFP
The 82371FB (PIIX) and 82371SB (PIIX3) PCI ISA IDE Xcelerators are multi-function PCI devices
implementing a PCI-to-ISA bridge function and an PCI IDE function. In addition, the PIIX3 implements a
Universal Serial Bus host/hub function. As a PCI-to-ISA bridge, the PIIX/PIIX3 integrates many common I/O
functions found in ISA-based PC systems—a seven-channel DMA controller, two 82C59 interrupt controllers,
an 8254 timer/counter, and power management support. In addition to compatible transfers, each DMA
channel supports type F transfers. Chip select decoding is provided for BIOS, real time clock, and keyboard
controller. Edge/Level interrupts and interrupt steering are supported for PCI plug and play compatibility. The
PIIX/PIIX3 supports two IDE connectors for up to four IDE devices providing an interface for IDE hard disks
and CD ROMs. The PIIX/PIIX3 provides motherboard plug and play compatibility. PIIX implements two
steerable DMA channels (including type F transfers) and up to two steerable interrupt lines. PIIX3 implements
one steerable interrupt line. The interrupt lines can be routed to any of the available ISA interrupts. Both
PIIX/PIIX3 implement a programmable chip select.
PIIX3 contains a Universal Serial Bus (USB) Host Controller that is UHCI compatible. The Host Controller’s
root hub has two programmable USB ports. PIIX3 also provides support for an external IOAPIC.
This document describes the PIIX3 Component. Unshaded areas describe the 82371FB PIIX. Shaded areas,
like this one, describe the PIIX3 operations that differ from the 82371FB PIIX.
© INTEL CORPORATION 1996, 1997
April 1997
Order Number: 290550-002




82371SB pdf, 반도체, 판매, 대치품
82371FB (PIIX) AND 82371SB (PIIX3)
E
2.2.19. SMIEN—SMI ENABLE REGISTER (Function 0) ....................................................................... 43
2.2.20. SEE—SYSTEM EVENT ENABLE REGISTER (Function 0) ...................................................... 44
2.2.21. FTMR—FAST OFF TIMER REGISTER (Function 0)................................................................. 45
2.2.22. SMIREQ—SMI REQUEST REGISTER (Function 0) ................................................................. 45
2.2.23. CTLTMR—CLOCK SCALE STPCLK# LOW TIMER (Function 0) .............................................. 46
2.2.24. CTHTMR—CLOCK SCALE STPCLK# HIGH TIMER (Function 0)............................................. 47
2.3. PCI Configuration Registers—IDE Interface (Function 1) ................................................................... 47
2.3.1. VID—Vendor Identification Register (Function 1) ........................................................................ 47
2.3.2. DID—DEVICE IDENTIFICATION REGISTER (Function 1) ......................................................... 47
2.3.3. PCICMD—COMMAND REGISTER (Function 1) ......................................................................... 48
2.3.4. PCISTS—PCI DEVICE STATUS REGISTER (Function 1) .......................................................... 48
2.3.5. RID—REVISION IDENTIFICATION REGISTER (Function 1)...................................................... 49
2.3.6. CLASSCCLASS CODE REGISTER (Function 1)..................................................................... 49
2.3.7. MLT—MASTER LATENCY TIMER REGISTER (Function 1) ...................................................... 49
2.3.8. HEDT—HEADER TYPE REGISTER (Function 1) ....................................................................... 50
2.3.9. BMIBA—BUS MASTER INTERFACE BASE ADDRESS REGISTER (Function 1) ...................... 50
2.3.10. IDETIM—IDE TIMING REGISTER (Function 1) ........................................................................ 51
2.3.11. SIDETIM—SLAVE IDE TIMING REGISTER (Function 1) (PIIX3 Only) ..................................... 52
2.4. PCI Configuration RegistersUniversal Serial Bus (Function 2) (PIIX3 Only).................................... 53
2.4.1. VID—VENDOR IDENTIFICATION REGISTER (Function 2) (PIIX3)............................................ 53
2.4.2. DIDDEVICE IDENTIFICATION REGISTER (Function 2) (PIIX3) ............................................. 54
2.4.3. PCICMDCOMMAND REGISTER (Function 2) (PIIX3) ............................................................. 54
2.4.4. DSDEVICE STATUS REGISTER (Function 2) (PIIX3)............................................................. 55
2.4.5. RIDREVISION IDENTIFICATION REGISTER (Function 2) (PIIX3).......................................... 55
2.4.6. CLASSCCLASS CODE REGISTER (Function 2) (PIIX3)......................................................... 56
2.4.7. MLTMASTER LATENCY TIMER REGISTER (Function 2) (PIIX3) .......................................... 56
2.4.8. HEDTHEADER TYPE REGISTER (Function 2) (PIIX3) ........................................................... 57
2.4.9. BASEADDI/O SPACE BASE ADDRESS (Function 2) (PIIX3) ................................................ 57
2.4.10. ILInterrupt Line Register (Function 2) (PIIX3)......................................................................... 57
2.4.11. INTRPINTERRUPT PIN (Function 2) (PIIX3) ......................................................................... 58
2.4.12. SBRNUMSERIAL BUS RELEASE NUMBER (Function 2) (PIIX3) ......................................... 58
2.4.13. MSTATMISCELLANEOUS STATUS REGISTER (Function 2) (PIIX3)................................... 58
2.4.14. LEGSUPLEGACY SUPPORT REGISTER (FUNCTION 2) (PIIX3) ........................................ 59
2.5. ISA-Compatible Registers .................................................................................................................. 61
2.5.1. DMA REGISTERS....................................................................................................................... 61
2.5.1.1. DCOM—DMA Command Register........................................................................................ 61
2.5.1.2. DCM—DMA Channel Mode Register.................................................................................... 61
2.5.1.3. DR—DMA Request Register................................................................................................. 62
2.5.1.4. Mask Register—Write Single Mask Bit ................................................................................. 63
2.5.1.5. Mask Register—Write All Mask Bits...................................................................................... 63
2.5.1.6. DS—DMA Status Register.................................................................................................... 64
2.5.1.7. DMA Base And Current Address Registers (8237 Compatible Segment).............................. 64
2.5.1.8. DMA Base And Current Byte/Word Count Registers (Compatible Segment) ........................ 65
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82371SB 전자부품, 판매, 대치품
E
REVISION HISTORY
Revision Date
May 1996
April 1997
82371FB (PIIX) AND 82371SB (PIIX3)
-001
-002
Version
Description
Initial Release
Included information from
Specification Update
Information in this document is provided in connection with Intel products. No license, express or implied,
by estoppel or otherwise, to any intellectual property rights is granted by this document or by the sale of
Intel products. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes
no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of
Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or
infringement of any patent, copyright or other intellectual property right. Intel products are not intended for
use in medical, life saving, or life sustaining applications. Intel retains the right to make changes to
specifications and product descriptions at any time, without notice. The Intel 82371FB and 82371SB may
contain design defects or errors known as errata. Which may cause the products to deviate from published
specifications. Such errata are not covered by Intel’s warranty. Current characterized errata are available in
“Intel 430FX TSC/TDP/PIIX Specification Update (Order#297733)and Intel 82371SB (PIIX3) PCI ISA IDE
Xcelerator Specification Update (Order#297658). Third-party brands and names are the property of their
respective owners.
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82371SB

82371FB (PIIX) AND 82371SB (PIIX3) PCI ISA IDE XCELERATOR

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