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82434NX 데이터시트 PDF




Intel Corporation에서 제조한 전자 부품 82434NX은 전자 산업 및 응용 분야에서
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부품번호 82434NX 기능
기능 PCI/ CACHE AND MEMORY CONTROLLER PCMC
제조업체 Intel Corporation
로고 Intel Corporation 로고


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82434NX 데이터시트, 핀배열, 회로
82434LX 82434NX PCI CACHE AND MEMORY
CONTROLLER (PCMC)
Y Supports the PentiumTM Processor at
iCOMPTM Index 510T60 MHz and iCOMP
Index 567T66 MHz
Y Supports the Pentium Processor at
iCOMP Index 735T90 MHz iCOMP Index
815T100 MHz and iCOMP Index 610T75
MHz
Y Supports Pipelined Addressing
Capability of the Pentium Processor
Y The 82430NX Drives 3 3V Signal Levels
on the CPU and Cache Interfaces
Y High Performance CPU PCI Memory
Interfaces via Posted Write and Read
Prefetch Buffers
Y Fully Synchronous PCI Interface with
Full Bus Master Capability
Y Supports the Pentium Processor
Internal Cache in Either Write-Through
or Write-Back Mode
Y Programmable Attribute Map of DOS
and BIOS Regions for System
Flexibility
Y Integrated Low Skew Clock Driver for
Distributing Host Clock
Y Integrated Second Level Cache
Controller
Integrated Cache Tag RAM
Write-Through and Write-Back Cache
Modes for the 82434LX
Write-Back for the 82434NX
82434NX Supports Low-Power Cache
Standby
Direct Mapped Organization
Supports Standard and Burst SRAMs
256-KByte and 512-KByte Sizes
Cache Hit Cycle of 3-1-1-1 on Reads
and Writes Using Burst SRAMs
Cache Hit Cycle of 3-2-2-2 on Reads
and 4-2-2-2 on Writes Using
Standard SRAMs
Y Integrated DRAM Controller
Supports 2 MBytes to 192 MBytes of
Cacheable Main Memory for the
82434LX
Supports 2 MBytes to 512 MBytes of
Cacheable Main Memory for the
82434NX
Supports DRAM Access Times of
70 ns and 60 ns
CPU Writes Posted to DRAM 4-1-1-1
Refresh Cycles Decoupled from ISA
Refresh to Reduce the DRAM
Access Latency
Six RAS Lines (82434LX)
Eight RAS Lines (82434NX)
Refresh by RAS -Only or CAS-
Before-RAS in Single or Burst
of Four
Y Host PCI Bridge
Translates CPU Cycles into PCI Bus
Cycles
Translates Back-to-Back Sequential
CPU Memory Writes into PCI Burst
Cycles
Burst Mode Writes to PCI in Zero PCI
Wait-States (i e Data Transfer Every
Cycle)
Full Concurrency Between CPU-to-
Main Memory and PCI-to-PCI
Transactions
Full Concurrency Between CPU-to-
Second Level Cache and PCI-to-Main
Memory Transactions
Same Cache and Memory System
Logic Design for ISA and EISA
Systems
Cache Snoop Filter Ensures Data
Consistency for PCI-to-Main Memory
Transactions
Y 208-Pin QFP Package
Other brands and names are the property of their respective owners
December 1994
Order Number 290479-004




82434NX pdf, 반도체, 판매, 대치품
82434LX 82434NX PCI CACHE AND MEMORY
CONTROLLER (PCMC)
CONTENTS
1 0 ARCHITECTURAL OVERVIEW
1 1 System Overview
1 1 1 BUS HIERARCHY CONCURRENT OPERATIONS
1 1 2 BUS BRIDGES
1 2 PCMC Overview
1 2 1 CACHE OPERATIONS
1 2 1 1 Cache Consistency
1 2 2 ADDRESS DATA PATHS
1 2 2 1 Read Write Buffers
1 2 3 HOST PCI BRIDGE OPERATIONS
1 2 4 DRAM MEMORY OPERATIONS
1 2 5 3 3V SIGNALS
2 0 SIGNAL DESCRIPTIONS
2 1 Host Interface
2 2 DRAM Interface
2 3 Cache Interface
2 4 PCI Interface
2 5 LBX Interface
2 6 Reset And Clock
3 0 REGISTER DESCRIPTION
3 1 I O Mapped Registers
3 1 1 CONFADD CONFIGURATION ADDRESS REGISTER
3 1 2 CSE CONFIGURATION SPACE ENABLE REGISTER
3 1 3 TRC TURBO-RESET CONTROL REGISTER
3 1 4 FORW FORWARD REGISTER
3 1 5 PMC PCI MECHANISM CONTROL REGISTER
3 1 6 CONFDATA CONFIGURATION DATA REGISTER
3 2 PCI Configuration Space Mapped Registers
3 2 1 CONFIGURATION SPACE ACCESS MECHANISM
3 2 1 1 Access Mechanism 1
3 2 1 2 Access Mechanism 2
3 2 2 VID VENDOR IDENTIFICATION REGISTER
3 2 3 DID DEVICE IDENTIFICATION REGISTER
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82434NX 전자부품, 판매, 대치품
CONTENTS
6 1 5 REFRESH
6 1 5 1 RAS -Only Refresh-Single
6 1 5 2 CAS -Before-RAS Refresh-Single
6 1 5 3 Hidden Refresh-Single
6 2 82434NX DRAM Interface
6 2 1 DRAM ADDRESS TRANSLATION
6 2 2 CYCLE TIMING SUMMARY
6 2 3 CPU TO DRAM BUS CYCLES
6 2 3 1 Burst DRAM Read Page Hit
6 2 3 2 Burst DRAM Read Page Miss
6 2 3 3 Burst DRAM Read Row Miss
6 2 3 4 Burst DRAM Write Page Hit
6 2 3 5 Burst DRAM Write Page Miss
6 2 3 6 Burst DRAM Write Row Miss
6 2 4 REFRESH
6 2 4 1 RAS -Only Refresh Single
6 2 4 2 CAS -before-RAS Refresh Single
6 2 4 3 Hidden Refresh-Single
7 0 PCI INTERFACE
7 1 PCI Interface Overview
7 2 CPU-to-PCI Cycles
7 2 1 CPU WRITE TO PCI
7 3 Register Access Cycles
7 3 1 CPU WRITE CYCLE TO PCMC INTERNAL REGISTER
7 3 2 CPU READ FROM PCMC INTERNAL REGISTER
7 3 3 CPU WRITE TO PCI DEVICE CONFIGURATION REGISTER
7 3 4 CPU READ FROM PCI DEVICE CONFIGURATION REGISTER
7 4 PCI-to-Main Memory Cycles
7 4 1 PCI MASTER WRITE TO MAIN MEMORY
7 4 2 PCI MASTER READ FROM MAIN MEMORY
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부품번호상세설명 및 기능제조사
82434NX

PCI/ CACHE AND MEMORY CONTROLLER PCMC

Intel Corporation
Intel Corporation

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