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부품번호 | 82801AA 기능 |
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기능 | 82801AB (ICH0) I/O Controller Hub | ||
제조업체 | Intel Corporation | ||
로고 | |||
전체 30 페이지수
Intel® 82801AA (ICH) and Intel®
82801AB (ICH0) I/O Controller
Hub
Datasheet
June 1999
Order Number: 290655-002
Intel® 82801AA (ICH) and Intel® 82801AB (ICH0) Simplified Block Diagram
AD[31:0]
C/BE[3:0]#
DEVSEL#
FRAME#
IRDY#
TRDY#
STOP#
PAR
(ICH) PERR#/GPIO7
REQ[0:3]#
(ICH) REQ[4]#
(ICH) REQ5#/REQB#/GPIO1
REQA#
GNT[0:3]#
(ICH) GNT[4]#
(ICH) GNT5#/GNTB#/GPIO17
GNTA#
PCICLK
PCIRST#
PLOCK#
SERR#
PME#
A20M#
CPUSLP#
FERR#
IGNNE#
INIT#
INTR
NMI
SMI#
STPCLK#
RCIN#
A20GATE
SERIRQ
PIRQ[A:D]#
IRQ[14:15]
APICCLK
APICD[1:0]
USBP1P
USBP1N
USBP0P
USBP0N
OC[1:0]#
RTCX1
RTCX2
VBIAS
CLK14
CLK48
CLK66
SPKR
RTCRST#
GPIO[0,1,5:13]
GPIO[16,17, 21:26]
GPIO[27:28]
PCI
Interface
CPU
Interface
Interrupt
USB
RTC
Clocks
Misc.
Signals
General
Purpose
I/O
IDE
Interface
Power
Mgnt
AC'97
Link
Hub
Interface
Firmware
Hub
LPC
Interface
SMBus
Interface
System
Mgnt
PDCS1#
SDCS1#
PDCS3#
SDCS3#
PDA[2:0]
SDA[2:0]
PDD[15:0]
SDD[15:0]
PDDREQ
SDDREQ
PDDACK#
SDDACK#
PDIOR#
SDIOR#
PDIOW#
SDIOW#
PIORDY
SIORDY
THRM#
SLP_S3/GPIO24
SLP_S5#
PWROK
PWRBTN#
RI#
RSMRST#
SUS_STAT#/GPIO25
SUSCLK/GPIO26 (ICH)
AC_RST#
AC_SYNC
AC_BIT_CLK
AC_SDOUT
AC_SDIN0
AC_SDIN1/GPIO9
HL[10:0] (ICH0); HL11:0] (ICH)
HL_STB
HL_STB#
HLCOMP
FWH[3:0]/LAD[3:0]
FWH[4]/LFRAME#
LAD[3:0]/FWH[4]
LFRAME#/FWH[4]
LDRQ[0]#
LDRQ[1]#/GPIO[8]
SMBDATA
SMBCLK
SMBALERT#/GPIO[11]
INTRUDER#
ALERTCLK/GPIO[27] (ICH)
ALERTDATA/GPIO[28] (ICH)
Note
1. Shaded areas: PERR#, REQ[4,5]#, GNT[4,5]#, HL[11], SUSCLK, ALERTCLK, and ALERTDATA are ICH
(82801AA) Signals only. The associated GPIOx signals are multiplexed on the ICH and are
non-multiplexed on ICH0.
2. General Purpose I/O Unit. Some GPIO signals are multiplexed with signals in other functional units.
iv 82801AA and 82801AB Datasheet
4페이지 5.2 LPC Bridge (with System & Management Functions) (D31:F0)....................5-4
5.2.1 LPC Interface ...................................................................................5-4
5.2.1.1 LPC Cycle Types..............................................................5-5
5.2.1.2 Start Field Definition .........................................................5-5
5.2.1.3 Cycle Type / Direction (CYCTYPE + DIR)........................5-6
5.2.1.4 SIZE..................................................................................5-6
5.2.1.5 SYNC................................................................................5-6
5.2.1.6 SYNC Time-out ................................................................5-7
5.2.1.7 SYNC Error Indication ......................................................5-7
5.2.1.8 LFRAME# Usage..............................................................5-7
5.2.1.9 I/O Cycles .........................................................................5-9
5.2.1.10 Bus Master Cycles............................................................5-9
5.2.1.11 Configuration and ICH Implications ..................................5-9
5.3 DMA Operation (D31:F0) ..............................................................................5-9
5.3.1 Channel Priority .............................................................................5-10
5.3.2 Address Compatibility Mode ..........................................................5-11
5.3.3 Summary of DMA Transfer Sizes ..................................................5-11
5.3.4 Autoinitialize...................................................................................5-12
5.3.5 Software Commands .....................................................................5-12
5.4 PCI DMA .....................................................................................................5-13
5.4.1 PCI DMA Expansion Protocol ........................................................5-13
5.4.2 PCI DMA Expansion Cycles ..........................................................5-14
5.4.3 DMA Addresses .............................................................................5-15
5.4.4 DMA Data Generation....................................................................5-15
5.4.5 DMA Byte Enable Generation........................................................5-15
5.4.6 DMA Cycle Termination .................................................................5-16
5.5 LPC DMA ....................................................................................................5-16
5.5.1 Asserting DMA Requests...............................................................5-16
5.5.2 Abandoning DMA Requests...........................................................5-17
5.5.3 General Flow of DMA Transfers ....................................................5-17
5.5.4 Terminal Count ..............................................................................5-18
5.5.5 Verify Mode....................................................................................5-18
5.5.6 DMA Request Deassertion ............................................................5-18
5.5.7 SYNC Field / LDRQ# Rules ...........................................................5-19
5.6 8254 Timers (D31:F0).................................................................................5-20
5.6.1 Timer Programming .......................................................................5-20
5.6.2 Reading from the Interval Timer ....................................................5-21
5.7 8259 Interrupt Controllers (PIC) (D31:F0)...................................................5-23
5.7.1 Interrupt Handling ..........................................................................5-23
5.7.2 Initialization Command Words (ICWx) ...........................................5-25
5.7.3 Operation Command Words (OCW) ..............................................5-26
5.7.4 Modes of Operation .......................................................................5-26
5.7.5 Masking Interrupts .........................................................................5-29
5.7.6 Steering PCI Interrupts ..................................................................5-29
5.8 Advanced Interrupt Controller (APIC) (D31:F0) ..........................................5-30
5.8.1 Interrupt Handling ..........................................................................5-30
5.8.2 Interrupt Mapping...........................................................................5-30
5.8.3 APIC Bus Functional Description...................................................5-31
5.8.3.1 Physical Characteristics of APIC ....................................5-31
5.8.3.2 APIC Bus Arbitration.......................................................5-31
5.8.3.3 Bus Message Formats....................................................5-32
82801AA and 82801AB Datasheet
vii
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부품번호 | 상세설명 및 기능 | 제조사 |
82801AA | 82801AB (ICH0) I/O Controller Hub | Intel Corporation |
82801AB | 82801AB (ICH0) I/O Controller Hub | Intel Corporation |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |