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부품번호 82C84A 기능
기능 CMOS Clock Generator Driver
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82C84A 데이터시트, 핀배열, 회로
82C84A
March 1997
CMOS Clock Generator Driver
Features
Description
• Generates the System Clock For CMOS or NMOS
Microprocessors
• Up to 25MHz Operation
• Uses a Parallel Mode Crystal Circuit or External
Frequency Source
• Provides Ready Synchronization
• Generates System Reset Output From Schmitt Trigger
Input
• TTL Compatible Inputs/Outputs
• Very Low Power Consumption
• Single 5V Power Supply
• Operating Temperature Ranges
- C82C84A . . . . . . . . . . . . . . . . . . . . . . . . .0oC to +70oC
- I82C84A . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC
- M82C84A . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
The Intersil 82C84A is a high performance CMOS Clock Generator-
driver which is designed to service the requirements of both CMOS
and NMOS microprocessors such as the 80C86, 80C88, 8086 and
the 8088. The chip contains a crystal controlled oscillator, a divide-by-
three counter and complete “Ready” synchronization and reset logic.
Static CMOS circuit design permits operation with an external fre-
quency source from DC to 25MHz. Crystal controlled operation to
25MHz is guaranteed with the use of a parallel, fundamental mode
crystal and two small load capacitors.
All inputs (except X1 and RES) are TTL compatible over tempera-
ture and voltage ranges.
Power consumption is a fraction of that of the equivalent bipolar cir-
cuits. This speed-power characteristic of CMOS permits the
designer to custom tailor his system design with respect to power
and/or speed requirements.
Ordering Information
PART
NUMBER
CP82C84A
IP82C84A
CS82C84A
IS82C84A
CD82C84A
ID82C84A
MD82C84A/B
8406801VA
MR82C84A/B
84068012A
TEMP. RANGE
0oC to +70oC
-40oC to +85oC
0oC to +70oC
-40oC to +85oC
0oC to +70oC
-40oC to +85oC
-55oC to +125oC
-55oC to +125oC
PACKAGE
PKG.
NO.
18 Ld PDIP E18.3
E18.3
20 Ld PLCC N20.35
N20.35
18 Ld CERDIP F18.3
F18.3
F18.3
SMD#
F18.3
20 Pad CLCC J20.A
SMD#
J20.A
Pinouts
82C84A (PDIP, CERDIP)
TOP VIEW
CSYNC 1
PCLK 2
AEN1 3
RDY1 4
READY 5
RDY2 6
AEN2 7
CLK 8
GND 9
18 VCC
17 X1
16 X2
15 ASYNC
14 EFI
13 F/C
12 OSC
11 RES
10 RESET
82C84A (PLCC, CLCC)
TOP VIEW
3 2 1 20 19
RDY1 4
READY 5
RDY2 6
AEN2 7
NC 8
18 X2
17 ASYNC
16 EFI
15 F/C
14 NC
9 10 11 12 13
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
4-287
File Number 2974.1




82C84A pdf, 반도체, 판매, 대치품
82C84A
Functional Description
Oscillator
The oscillator circuit of the 82C84A is designed primarily for
use with an external parallel resonant, fundamental mode
crystal from which the basic operating frequency is derived.
The crystal frequency should be selected at three times the
required CPU clock. X1 and X2 are the two crystal input
crystal connections. For the most stable operation of the
oscillator (OSC) output circuit, two capacitors (C1 = C2) as
shown in the waveform figures are recommended. The out-
put of the oscillator is buffered and brought out on OSC so
that other system timing signals can be derived from this sta-
ble, crystal-controlled source.
TABLE 1. CRYSTAL SPECIFICATIONS
PARAMETER
TYPICAL CRYSTAL SPEC
Frequency
2.4 - 25MHz, Fundamental, “AT” cut
Type of Operation
Parallel
Unwanted Modes
6dB (Minimum)
Load Capacitance
18 - 32pF
Capacitors C1, C2 are chosen such that their combined
capacitance
CT = C-C----11-----+x-----CC----22-- (Including stray capacitance)
matches the load capacitance as specified by the crystal
manufacturer. This ensures operation within the frequency
tolerance specified by the crystal manufacturer.
Clock Generator
The clock generator consists of a synchronous divide-by-
three counter with a special clear input that inhibits the
counting. This clear input (CSYNC) allows the output clock
to be synchronized with an external event (such as another
82C84A clock). It is necessary to synchronize the CSYNC
input to the EFI clock external to the 82C84A. This is accom-
plished with two flip-flops. (See Figure 1). The counter out-
put is a 33% duty cycle clock at one-third the input
frequency.
NOTE: The F/C input is a strapping pin that selects either the crystal
oscillator or the EFI input as the clock for the ÷ 3 counter. If
the EFI input is selected as the clock source, the oscillator
section can be used independently for another clock source.
Output is taken from OSC.
Clock Outputs
The CLK output is a 33% duty cycle clock driver designed to
drive the 80C86, 80C88 processors directly. PCLK is a periph-
eral clock signal whose output frequency is 1/2 that of CLK.
PCLK has a 50% duty cycle.
Reset Logic
The reset logic provides a Schmitt trigger input (RES) and a
synchronizing flip-flop to generate the reset timing. The reset
signal is synchronized to the falling edge of CLK. A simple RC
network can be used to provide power-on reset by utilizing this
function of the 82C84A.
READY Synchronization
Two READY input (RDY1, RDY2) are provided to accommo-
date two system busses. Each input has a qualifier (AEN1 and
AEN2, respectively). The AEN signals validate their respective
RDY signals. If a Multi-Master system is not being used the
AEN pin should be tied LOW.
Synchronization is required for all asynchronous active-going
edges of either RDY input to guarantee that the RDY setup
and hold times are met. Inactive-going edges of RDY in nor-
mally ready systems do not require synchronization but must
satisfy RDY setup and hold as a matter of proper system
design.
The ASYNC input defines two modes of READY synchroniza-
tion operation.
When ASYNC is LOW, two stages of synchronization are pro-
vided for active READY input signals. Positive-going asynchro-
nous READY inputs will first be synchronized to flip-flop one of
the rising edge of CLK (requiring a setup time tR1VCH) and
the synchronized to flip-flop two at the next falling edge of
CLK, after which time the READY output will go active (HIGH).
Negative-going asynchronous READY inputs will be synchro-
nized directly to flip-flop two at the falling edge of CLK, after
which the READY output will go inactive. This mode of opera-
tion is intended for use by asynchronous (normally not ready)
devices in the system which cannot be guaranteed by design
to meet the required RDY setup timing, TR1VCL, on each bus
cycle.
When ASYNC is high or left open, the first READY flip-flop is
bypassed in the READY synchronization logic. READY inputs
are synchronized by flip-flop two on the falling edge of CLK
before they are presented to the processor. This mode is avail-
able for synchronous devices that can be guaranteed to meet
the required RDY setup time.
ASYNC can be changed on every bus cycle to select the
appropriate mode of synchronization for each device in the
system.
CLOCK
SYNCHRONIZE
EFI
DQ
>
D
Q
>
EFI
82C84A
CSYNC
(TO OTHER 82C84As)
NOTE: If EFI input is used, then crystal input X1 must be tied to VCC or GND and X2 should be left open. If the crystal inputs are used,
then EFI should be tied to VCC or GND.
FIGURE 1. CSYNC SYNCHRONIZATION
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82C84A 전자부품, 판매, 대치품
Timing Waveforms
82C84A
NAME
EFI
I/O
I
OSC O
CLK O
PCLK O
CSYNC I
RES I
RESET O
(3) tELEL
(13)
tEHYL
(14)
tYHYL
tOLCH
(29)
tCH1CH2
(20)
tYHEH
(12)
tCL2CL1
(21)
(30)
tOLCL
tELEH
(2)
(1) tEHEL
tCLPH
(27)
tPLPH
(23)
(19)
tCLCH
(17) tCLCL
(22)
tPHPL
(16) (15)
tCLI1H tI1HCL
tCHCL
(18)
tCLPL
(28)
(26)
tCLIL
NOTE: All timing measurements are made at 1.5V, unless otherwise noted.
FIGURE 2. WAVEFORMS FOR CLOCKS AND RESETS SIGNALS
CLK
tCLR1X
(7)
tR1VCH
RDY1, 2
(5)
(10)
tA1VR1V
AEN1, 2
ASYNC
tAYVCL
(8)
tCLAYX
(9)
READY
(25)
tRYHCH
tCLR1X
tR1VCL
(6)
(7)
tCLA1X
(11)
(24) tRYLCL
FIGURE 3. WAVEFORMS FOR READY SIGNALS (FOR ASYNCHRONOUS DEVICES)
CLK
RDY 1, 2
AEN1, 2
ASYNC
tCLR1X
(7)
(4) tR1VCL
tA1VRIV (10)
(8) tAYVCL
tCLAYX
(9)
READY
(25)
tRYHCH
tCLR1X
(7)
tCLA1X
(11)
tR1VCL
(6)
(24)
tRYLCL
FIGURE 4. WAVEFORMS FOR READY SIGNALS (FOR SYNCHRONOUS DEVICES)
4-293

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관련 데이터시트

부품번호상세설명 및 기능제조사
82C84

CMOS Clock Generator Driver

Intersil Corporation
Intersil Corporation
82C84A

CMOS Clock Generator Driver

Intersil Corporation
Intersil Corporation

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