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부품번호 8403602JA 기능
기능 2K x 8 Asynchronous CMOS Static RAM
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8403602JA 데이터시트, 핀배열, 회로
HM-65162
March 1997
2K x 8 Asynchronous
CMOS Static RAM
Features
• Fast Access Time. . . . . . . . . . . . . . . . . . . . 70/90ns Max
• Low Standby Current. . . . . . . . . . . . . . . . . . . .50µA Max
• Low Operating Current . . . . . . . . . . . . . . . . . 70mA Max
• Data Retention at 2.0V . . . . . . . . . . . . . . . . . . .20µA Max
• TTL Compatible Inputs and Outputs
• JEDEC Approved Pinout (2716, 6116 Type)
• No Clocks or Strobes Required
• Equal Cycle and Access Time
• Single 5V Supply
• Gated Inputs
• No Pull-Up or Pull-Down Resistors Required
Description
The HM-65162 is a CMOS 2048 x 8 Static Random Access
Memory manufactured using the Intersil Advanced SAJI V
process. The device utilizes asynchronous circuit design for
fast cycle time and ease of use. The pinout is the JEDEC 24
pin DIP, and 32 pad 8-bit wide standard which allows easy
memory board layouts flexible to accommodate a variety of
industry standard PROMs, RAMs, ROMs and EPROMs. The
HM-65162 is ideally suited for use in microprocessor based
systems with its 8-bit word length organization. The conve-
nient output enable also simplifies the bus interface by allow-
ing the data outputs to be controlled independent of the chip
enable. Gated inputs lower operating current and also elimi-
nate the need for pull-up or pull-down resistors.
Ordering Information
PACKAGE
CERDIP
JAN#
SMD#
CLCC
SMD#
TEMP. RANGE
-40oC to +85oC
-55oC to +125oC
-55oC to +125oC
-40oC to +85oC
-55oC to 125oC
70ns/20µA (NOTE 1)
HM1-65162B-9
29110BJA
8403606JA
HM4-65162B-9
8403606ZA
NOTE:
1. Access time/data retention supply current.
90ns/40µA (NOTE 1)
HM1-65162-9
29104BJA
8403602JA
HM4-65162-9
8403602ZA
90ns/300µA (NOTE 1)
HM1-65162C-9
-
8403603JA
HM4-65162C-9
8403603ZA
PKG. NO.
F24.6
F24.6
F24.6
J32.A
J32.A
Pinouts
HM-65162
(CERDIP)
TOP VIEW
HM-65162
(CLCC)
TOP VIEW
PIN DESCRIPTION
A7 1
A6 2
A5 3
A4 4
A3 5
A2 6
A1 7
A0 8
DQ0 9
DQ1 10
DQ2 11
GND 12
24 VCC
23 A8
22 A9
21 W
20 G
19 A10
18 E
17 DQ7
16 DQ6
15 DQ5
14 DQ4
13 DQ3
4 3 2 1 32 31 30
A6 5
29 A8
A5 6
28 A9
A4 7
27 NC
A3 8
26 W
A2 9
25 G
A1 10
24 A10
A0 11
23 E
NC 12
22 DQ7
DQ0 13
21 DQ6
14 15 16 17 18 19 20
NC No Connect
A0 - A10 Address Input
E Chip Enable/Power Down
VSS/GND Ground
DQ0 - DQ7 Data In/Data Out
VCC
W
Power (+5V)
Write Enable
G Output Enable
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
6-1
File Number 3000.1




8403602JA pdf, 반도체, 판매, 대치품
HM-65162
AC Electrical Specifications VCC = 5V ±10%, TA = -40oC to +85oC (HM-65162S-9, HM-65162B-9, HM65162-9, HM-65162C-9)
LIMITS
HM-65162S-9 HM-65162B-9 HM-65162-9 HM-65162C-9
SYMBOL
PARAMETER
MIN MAX MIN MAX MIN MAX MIN MAX UNITS CONDITIONS
READ CYCLE
(1) TAVAX Read Cycle Time
55 - 70 - 90 - 90 -
ns (Notes 1, 3)
(2) TAVQV Address Access Time - 55 - 70 - 90 - 90 ns (Notes 1, 3, 4)
(3) TELQV
Chip Enable Access
Time
- 55 - 70 - 90 - 90 ns (Notes 1, 3)
(4) TELQX
Chip Enable Output
Enable Time
5 - 5 - 5 - 5 - ns (Notes 2, 3)
(5) TGLQV Output Enable Access
-
35
-
50
-
65
-
65
ns
(Notes 1, 3)
Time
(6) TGLQX Output Enable Output
5
-
5
-
5
-
5
-
ns (Notes 2, 3)
Enable Time
(7) TEHQZ
Chip Enable Output
Disable Time
- 35 - 35 - 50 - 50 ns (Notes 2, 3)
(8) TGHQZ Output Enable Output - 30 - 35 - 40 - 40 ns (Notes 2, 3)
Disable Time
(9) TAVQX
Output Hold From
Address Change
5 - 5 - 5 - 5 - ns (Notes 1, 3)
WRITE CYCLE
(10) TAVAX Write Cycle Time
55 - 70 - 90 - 90 -
ns (Notes 1, 3)
(11) TELWH Chip Selection to End of 45 - 45 - 55 - 55 -
Write
ns (Notes 1, 3)
(12) TAVWL Address Setup Time 5 - 10 - 10 - 10 - ns (Notes 1, 3)
(13) TWLWH Write Enable Pulse
Width
40 - 40 - 55 - 55 -
ns (Notes 1, 3)
(14) TWHAX Write Enable Read
Setup Time
10 - 10 - 10 - 10 -
ns (Notes 1, 3)
(15) TGHQZ Output Enable Output - 30 - 35 - 40 - 40 ns (Notes 2, 3)
Disable Time
(16) TWLQZ Write Enable Output
Disable Time
- 30 - 40 - 50 - 50 ns (Notes 2, 3)
(17) TDVWH Data Setup Time
25 - 30 - 30 - 30 -
ns (Notes 1, 3)
(18) TWHDX Data Hold Time
10 - 10 - 15 - 15 -
ns (Notes 1, 3)
(19) TWHQX Write Enable Output
Enable Time
0-0-0-0-
ns (Notes 1, 3)
(20) TWLEH Write Enable Pulse
Setup Time
45 - 40 - 55 - 55 -
ns (Notes 1, 3)
(21) TDVEH
Chip Enable Data
Setup Time
25 - 30 - 30 - 30 -
ns (Notes 1, 3)
(22) TAVWH Address Valid to End of 45 - 50 - 65 - 65 -
Write
ns (Notes 1, 3)
NOTES:
1. Input pulse levels: 0 to 3.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load: 1 TTL gate
equivalent and CL = 50pF (min) - for CL greater than 50pF, access time is derated by 0.15ns per pF.
2. Tested at initial design and after major design changes.
3. VCC = 4.5 and 5.5V.
4. TAVQV = TELQV + TAVEL.
6-4

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8403602JA 전자부품, 판매, 대치품
HM-65162
Typical Performance Curve
-3
VCC = 2.0V
-4
-5
-6
-7
-8
-9
-10
-11
-12
-55 -35 -15
5
25 45 65 85
TA (oC)
FIGURE 5. TYPICAL ICCDR vs TA
105 125
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (407) 724-7000
FAX: (407) 724-7240
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
ASIA
Intersil (Taiwan) Ltd.
Taiwan Limited
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
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부품번호상세설명 및 기능제조사
8403602JA

2K x 8 Asynchronous CMOS Static RAM

Intersil Corporation
Intersil Corporation

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