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8403607ZA 데이터시트 PDF




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부품번호 8403607ZA 기능
기능 2K x 8 CMOS RAM
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8403607ZA 데이터시트, 핀배열, 회로
HM-6516
March 1997
2K x 8 CMOS RAM
Features
Description
• Low Power Standby . . . . . . . . . . . . . . . . . . . 275µW Max
• Low Power Operation . . . . . . . . . . . . . 55mW/MHz Max
• Fast Access Time. . . . . . . . . . . . . . . . . . 120/200ns Max
• Industry Standard Pinout
• Single Supply . . . . . . . . . . . . . . . . . . . . . . . . . . 5.0V VCC
• TTL Compatible
• Static Memory Cells
• High Output Drive
• On-Chip Address Latches
• Easy Microprocessor Interfacing
The HM-6516 is a CMOS 2048 x 8 Static Random Access
Memory. Extremely low power operation is achieved by the
use of complementary MOS design techniques. This low
power is further enhanced by the use of synchronous circuit
techniques that keep the active (operating) power low, which
also gives fast access times. The pinout of the HM-6516 is
the popular 24 pin, 8-bit wide JEDEC standard, which allows
easy memory board layouts, flexible enough to accommo-
date a variety of PROMs, RAMS, EPROMs, and ROMs.
The HM-6516 is ideally suited for use in microprocessor
based systems. The byte wide organization simplifies the
memory array design, and keeps operating power down to a
minimum, because only one device is enabled at a time. The
address latches allow very simple interfacing to recent gen-
eration microprocessors which employ a multiplexed
address/data bus. The convenient output enable control also
simplifies multiplexed bus interfacing by allowing the data
outputs to be controlled independent of the chip enable.
Ordering Information
120ns
HM1-6516B-9
-
8403607JA
-
8403607ZA
Pinouts
HM-6516
(CERDIP)
TOP VIEW
200ns
HM1-6516-9
29102BJA
8403601JA
HM4-6516-9
8403601ZA
TEMP. RANGE
-40oC to +85oC
-55oC to +125oC
-55oC to +125oC
-40oC to +85oC
-55oC to +125oC
PACKAGE
CERDIP
JAN#
SMD#
CLCC
SMD#
HM-6516
(CLCC)
TOP VIEW
PKG. NO.
F24.6
F24.6
F24.6
J32.A
J32.A
A7 1
A6 2
A5 3
A4 4
A3 5
A2 6
A1 7
A0 8
DQ0 9
DQ1 10
DQ2 11
GND 12
24 VCC
23 A8
22 A9
21 W
20 G
19 A10
18 E
17 DQ7
16 DQ6
15 DQ5
14 DQ4
13 DQ3
4 3 2 1 32 31 30
A6 5
29 A8
A5 6
28 A9
A4 7
27 NC
A3 8
26 W
A2 9
25 G
A1 10
24 A10
A0 11
23 E
NC 12
22 DQ7
DQ0 13
21 DQ6
14 15 16 17 18 19 20
PIN DESCRIPTION
NC No Connect
A0 - A10 Address Inputs
E Chip Enable/Power Down
VSS/GND Ground
DQ0 - DQ7 Data In/Data Out
VCC
W
Power (+5V)
Write Enable
G Output Enable
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
6-1
File Number 2998.1




8403607ZA pdf, 반도체, 판매, 대치품
HM-6516
AC Electrical Specifications VCC = 5V ±10%; TA = -40oC to +85oC (HM-6516B-9, HM-6516-9)
LIMITS
SYMBOL
PARAMETER
HM-6516B-9
MIN MAX
HM-6516-9
MIN MAX
UNITS
TEST
CONDITIONS
(1) TELQV
Chip Enable Access Time
- 120 - 200 ns
(Notes 1, 3)
(2) TAVQV
Address Access Time
- 120 - 200 ns (Notes 1, 3, 4)
(3) TELQX
Chip Enable Output Enable Time
10 - 10 -
ns (Notes 2, 3)
(4) TWLQZ Write Enable Output Disable Time
- 50 - 80 ns
(Notes 2, 3)
(5) TEHQZ
Chip Enable Output Disable Time
- 50 - 80 ns
(Notes 2, 3)
(6) TGLQV
Output Enable Output Valid Time
- 80 - 80 ns
(Notes 1, 3)
(7) TGLQX
Output Enable Output Enable Time
10 - 10 -
ns (Notes 2, 3)
(8) TGHQZ Output Enable Output DisableTime
- 50 - 80 ns
(Notes 2, 3)
(9) TELEH
Chip Enable Pulse Negative Width
120 - 200 -
ns (Notes 1, 3)
(10) TEHEL
Chip Enable Pulse Positive Width
50 - 80 -
ns (Notes 1, 3)
(11) TAVEL
Address Setup Time
0 - 0 - ns (Notes 1, 3)
(12) TELAX
Address Hold Time
30 - 50 -
ns (Notes 1, 3)
(13) TWLWH Write Enable Pulse Width
120 - 200 -
ns (Notes 1, 3)
(14) TWLEH Write Enable Pulse Setup Time
120 - 200 -
ns (Notes 1, 3)
(15) TELWH Write Enable Pulse Hold Time
120 - 200 -
ns (Notes 1, 3)
(16) TDVWH Data Setup Time
50 - 80 -
ns (Notes 1, 3)
(17) TWHDX Data Hold Time
10 - 10 -
ns (Notes 1, 3)
(18) TELEL
Read or Write Cycle Time
170 - 280 -
ns (Notes 1, 3)
NOTES:
1. Input pulse levels: 0.8V to VCC - 2.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load:
1 TTL gate equivalent, CL = 50pF (min) - for CL greater than 50pF, access time is derated by 0.15ns per pF.
2. Tested at initial design and after major design changes.
3. VCC = 4.5V and 5.5V.
4. TAVQV = TELQV + TAVEL.
6-4

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부품번호상세설명 및 기능제조사
8403607ZA

2K x 8 CMOS RAM

Intersil Corporation
Intersil Corporation

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