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기능 CMOS 16-Bit Microprocessor
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8405202QA 데이터시트, 핀배열, 회로
80C86
March 1997
CMOS 16-Bit Microprocessor
[ /Title
(80C86
)
/Sub-
ject
(CMO
S 16-
Bit
Micro-
proces-
sor)
/Autho
r ()
/Key-
words
(Inter-
sil
Corpo-
ration,
Inter-
sil
Corpo-
ration,
16 Bit
uP,
micro-
proces-
sor,
8086,
PC)
/Cre-
Features
Description
• Compatible with NMOS 8086
• Completely Static CMOS Design
- DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5MHz (80C86)
- DC . . . . . . . . . . . . . . . . . . . . . . . . . . . .8MHz (80C86-2)
• Low Power Operation
- lCCSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . .500µA Max
- ICCOP . . . . . . . . . . . . . . . . . . . . . . . . . 10mA/MHz Typ
• 1MByte of Direct Memory Addressing Capability
• 24 Operand Addressing Modes
• Bit, Byte, Word and Block Move Operations
• 8-Bit and 16-Bit Signed/Unsigned Arithmetic
- Binary, or Decimal
- Multiply and Divide
• Wide Operating Temperature Range
- C80C86 . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to +70oC
- l80C86 . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC
- M80C86 . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
The Intersil 80C86 high performance 16-bit CMOS CPU is
manufactured using a self-aligned silicon gate CMOS pro-
cess (Scaled SAJI IV). Two modes of operation, minimum for
small systems and maximum for larger applications such as
multiprocessing, allow user configuration to achieve the
highest performance level. Full TTL compatibility (with the
exception of CLOCK) and industry standard operation allow
use of existing NMOS 8086 hardware and software designs.
Ordering Information
PACKAGE
PDIP
PLCC
CERDIP
SMD#
CLCC
SMD#
TEMP. RANGE 5MHz
8MHz
PKG.
NO.
0oC to +70oC CP80C86 CP80C86-2 E40.6
-40oC to +85oC lP80C86 IP80C86-2 E40.6
0oC to +70oC CS80C86 CS80C86-2 N44.65
-40oC to +85oC lS80C86 IS80C86-2 N44.65
0oC to +70oC CD80C86 CD80C86-2 F40.6
-40oC to +85oC ID80C86 ID80C86-2 F40.6
-55oC to +125oC MD80C86/B MD80C86- F40.6
2/B
-55oC to +125oC 8405201QA 8405202QA F40.6
-55oC to +125oC MR80C86/B MR80C86- J44.A
2/B
-55oC to +125oC 8405201XA 8405202XA J44.A
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
3-141
File Number 2957.1




8405202QA pdf, 반도체, 판매, 대치품
80C86
Pin Description
The following pin function descriptions are for 80C86 systems in either minimum or maximum mode. The “Local Bus” in these description is
the direct multiplexed bus interface connection to the 80C86 (without regard to additional bus buffers).
SYMBOL
PIN
NUMBER
TYPE
DESCRIPTION
AD15-AD0 2-16, 39
I/O ADDRESS DATA BUS: These lines constitute the time multiplexed memory/lO address (T1) and
data (T2, T3, TW, T4) bus. A0 is analogous to BHE for the lower byte of the data bus, pins D7-
D0. It is LOW during Ti when a byte is to be transferred on the lower portion of the bus in memory
or I/O operations. Eight-bit oriented devices tied to the lower half would normally use A0 to con-
dition chip select functions (See BHE). These lines are active HIGH and are held at high imped-
ance to the last valid logic level during interrupt acknowledge and local bus “hold acknowledge”
or “grant sequence”.
A19/S6
A18/S5
A17/S4
A16/S3
35-38
O ADDRESS/STATUS: During T1, these are the four most significant address lines for memory op-
erations. During I/O operations these lines are LOW. During memory and I/O operations, status
information is available on these lines during T2, T3, TW, T4. S6 is always LOW. The status of
the interrupt enable FLAG bit (S5) is updated at the beginning of each clock cycle. S4 and S3
are encoded as shown.
This information indicates which segment register is presently being used for data accessing.
These lines are held at high impedance to the last valid logic level during local bus “hold ac-
knowledge” or “grant sequence”.
S4 S3 CHARACTERISTICS
0 0 Alternate Data
0 1 Stack
1 0 Code or None
1 1 Data
BHE/S7
34
O BUS HIGH ENABLE/STATUS: During T1 the bus high enable signal (BHE) should be used to
enable data onto the most significant half of the data bus, pins D15-D8. Eight bit oriented devices
tied to the upper half of the bus would normally use BHE to condition chip select functions. BHE
is LOW during T1 for read, write, and interrupt acknowledge cycles when a byte is to be trans-
ferred on the high portion of the bus. The S7 status information is available during T2, T3 and
T4. The signal is active LOW, and is held at high impedance to the last valid logic level during
interrupt acknowledge and local bus “hold acknowledge” or “grant sequence”, it is LOW during
T1 for the first interrupt acknowledge cycle.
BHE
0
0
1
1
A0 CHARACTERISTICS
0 Whole Word
1 Upper Byte From/to Odd Address
0 Lower Byte From/to Even address
1 None
RD 32
READY
22
O READ: Read strobe indicates that the processor is performing a memory or I/O read cycle, de-
pending on the state of the M/IO or S2 pin. This signal is used to read devices which reside on
the 80C86 local bus. RD is active LOW during T2, T3 and TW of any read cycle, and is guaran-
teed to remain HIGH in T2 until the 80C86 local bus has floated.
This line is held at a high impedance logic one state during “hold acknowledge” or “grand se-
quence”.
I READY: is the acknowledgment from the addressed memory or I/O device that will complete the
data transfer. The RDY signal from memory or I/O is synchronized by the 82C84A Clock Gener-
ator to form READY. This signal is active HIGH. The 80C86 READY input is not synchronized.
Correct operation is not guaranteed if the Setup and Hold Times are not met.
3-144

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8405202QA 전자부품, 판매, 대치품
80C86
Maximum Mode System (Continued)
The following pin function descriptions are for the 80C86 system in maximum mode (i.e., MN/MX - GND). Only the pin functions which are
unique to maximum mode are described below.
SYMBOL
PIN
NUMBER
TYPE
DESCRIPTION
RQ/GT0
RQ/GT1
31, 30
I/O REQUEST/GRANT: pins are used by other local bus masters to force the processor to release
the local bus at the end of the processor’s current bus cycle. Each pin is bidirectional with
RQ/GTO having higher priority than RQ/GT1. RQ/GT has an internal pull-up bus hold device so
it may be left unconnected. The request/grant sequence is as follows (see RQ/GT Sequence
Timing)
1. A pulse of 1 CLK wide from another local bus master indicates a local bus request (“hold”)
to the 80C86 (pulse 1).
2. During a T4 or TI clock cycle, a pulse 1 CLK wide from the 80C86 to the requesting master
(pulse 2) indicates that the 80C86 has allowed the local bus to float and that it will enter the
“grant sequence” state at the next CLK. The CPU’s bus interface unit is disconnected logi-
cally from the local bus during “grant sequence”.
3. A pulse 1 CLK wide from the requesting master indicates to the 80C86 (pulse 3) that the
“hold” request is about to end and that the 80C86 can reclaim the local bus at the next CLK.
The CPU then enters T4 (or TI if no bus cycles pending).
Each Master-Master exchange of the local bus is a sequence of 3 pulses. There must be one
idle CLK cycle after each bus exchange. Pulses are active low.
If the request is made while the CPU is performing a memory cycle, it will release the local
bus during T4 of the cycle when all the following conditions are met:
1. Request occurs on or before T2.
2. Current cycle is not the low byte of a word (on an odd address).
3. Current cycle is not the first acknowledge of an interrupt acknowledge sequence.
4. A locked instruction is not currently executing.
If the local bus is idle when the request is made the two possible events will follow:
1. Local bus will be released during the next cycle.
2. A memory cycle will start within three clocks. Now the four rules for a currently active memory
cycle apply with condition number 1 already satisfied.
LOCK
29
O LOCK: output indicates that other system bus masters are not to gain control of the system bus
while LOCK is active LOW. The LOCK signal is activated by the “LOCK” prefix instruction and
remains active until the completion of the next instruction. This signal is active LOW, and is held
at a high impedance logic one state during “grant sequence”. In MAX mode, LOCK is automat-
ically generated during T2 of the first INTA cycle and removed during T2 of the second INTA
cycle.
QS1, QSO
24, 25
O QUEUE STATUS: The queue status is valid during the CLK cycle after which the queue opera-
tion is performed.
QS1 and QS0 provide status to allow external tracking of the internal 80C86 instruction queue.
Note that QS1, QS0 never become high impedance.
QSI QSO
0 0 No Operation
0 1 First byte of op code from queue
1 0 Empty the queue
1 1 Subsequent byte from queue
3-147

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부품번호상세설명 및 기능제조사
8405202QA

CMOS 16-Bit Microprocessor

Intersil Corporation
Intersil Corporation

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