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부품번호 84069012A 기능
기능 CMOS Bus Controller
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84069012A 데이터시트, 핀배열, 회로
82C88
March 1997
CMOS Bus Controller
Features
Description
• Compatible with Bipolar 8288
• Performance Compatible with:
- 80C86/80C88 . . . . . . . . . . . . . . . . . . . . . . . . . .(5/8MHz)
- 80186/80188 . . . . . . . . . . . . . . . . . . . . . . . . . .(6/8MHz)
- 8086/8088 . . . . . . . . . . . . . . . . . . . . . . . . . . . .(5/8MHz)
- 8089
• Provides Advanced Commands for Multi-Master
Busses
• Three-State Command Outputs
• Bipolar Drive Capability
• Scaled SAJI IV CMOS Process
• Single 5V Power Supply
• Low Power Operation
- ICCSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10µA (Max)
- ICCOP . . . . . . . . . . . . . . . . . . . . . . . . .1mA/MHz (Max)
• Operating Temperature Ranges
- C82C88 . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to +70oC
- I82C88 . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC
- M82C88 . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
The Intersil 82C88 is a high performance CMOS Bus Con-
troller manufactured using a self-aligned silicon gate CMOS
process (Scaled SAJI IV). The 82C88 provides the control
and command timing signals for 80C86, 80C88, 8086, 8088,
8089, 80186, and 80188 based systems. The high output
drive capability of the 82C88 eliminates the need for addi-
tional bus drivers.
Static CMOS circuit design insures low operating power. The
Intersil advanced SAJI process results in performance equal
to or greater than existing equivalent products at a significant
power savings.
Ordering Information
PART NUMBER
CP82C88
CP82C88-10
IP82C88
CS82C88
IS82C88
CD82C88
ID82C88
MD82C88/B
8406901RA
MR82C88/B
84069012A
PACKAGE
20 Ld PDIP
20 Ld
PLCC
20 Ld
CERDIP
SMD#
20 Pad
CLCC
SMD#
TEMPERATURE
RANGE
0oC to +70oC
0oC to +70oC
-40oC to +85oC
0oC to +70oC
-40oC to +85oC
0oC to +70oC
-40oC to +85oC
-55oC to +125oC
-55oC to +125oC
PKG.
NO.
E20.3
E20.3
E20.3
N20.35
N20.35
F20.3
F20.3
F20.3
F20.3
J20.A
J20.A
Pinouts
20 LEAD PDIP, CERDIP
TOP VIEW
IOB 1
CLK 2
S1 3
DT/ R 4
ALE 5
AEN 6
MRDC 7
AMWC 8
MWTC 9
GND 10
20 VCC
19 S0
18 S2
17 MCE/PDEN
16 DEN
15 CEN
14 INTA
13 IORC
12 AIOWC
11 IOWC
20 LEAD PLCC, CLCC
TOP VIEW
3 2 1 20 19
DT/ R 4
ALE 5
AEN 6
18 S2
17 MCE/PDEN
16 DEN
MRDC 7
15 CEN
AMWC 8
14 INTA
9 10 11 12 13
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
4-333
File Number 2979.1




84069012A pdf, 반도체, 판매, 대치품
82C88
INTA (Interrupt Acknowledge) acts as an I/O read during an
interrupt cycle. Its purpose is to inform an interrupting device
that its interrupt is being acknowledged and that it should
place vectoring information onto the data bus.
The command outputs are:
MRDC - Memory Read Command
MWTC - Memory Write Command
IORC - I/O Read Command
IOWC - I/O Write Command
AMWC - Advanced Memory Write Command
AIOWC - Advanced I/O Write Command
INTA - Interrupt Acknowledge
Control Outputs
The control outputs of the 82C88 are Data Enable (DEN),
Data Transmit/Receive (DT/R) and Master Cascade Enable/
Peripheral Data Enable (MCE/PDEN). The DEN signal
determines when the external bus should be enabled onto
the local bus and the DT/R determines the direction of data
transfer. These two signals usually go to the chip select and
direction pins of a transceiver.
The MCE/PDEN pin changes function with the two modes of
the 82C88. When the 82C88 is in the IOB mode (IOB HIGH),
the PDEN signal serves as a dedicated data enable signal
for the I/O or Peripheral System bus.
Interrupt Acknowledge and MCE
The MCE signal is used during an interrupt acknowledge
cycle if the 82C88 is in the System Bus mode (IOB LOW).
During any interrupt sequence, there are two interrupt
acknowledge cycles that occur back to back. During the first
interrupt cycle no data or address transfers take place. Logic
should be provided to mask off MCE during this cycle. Just
before the second cycle begins the MCE signal gates a mas-
ter Priority Interrupt Controller’s (PIC) cascade address onto
the processor’s local bus where ALE (Address Latch Enable)
strobes it into the address latches. On the leading edge of
the second interrupt cycle, the addressed slave PIC gates an
interrupt vector onto the system data bus where it is read by
the processor.
If the system contains only one PIC, the MCE signal is not
used. In this case, the second Interrupt Acknowledge signal
gates the interrupt vector onto the processor bus.
Address Latch Enable and Halt
Address Latch Enable (ALE) occurs during each machine
cycle and serves to strobe the current address into the
82C82/82C83H address latches. ALE also serves to strobe
the status (S0, S1, S2) into a latch for halt state decoding.
Command Enable
The Command Enable (CEN) input acts as a command
qualifier for the 82C88. If the CEN pin is high, the 82C88
functions normally. If the CEN pin is pulled LOW, all com-
mand lines are held in their inactive state (not three-state).
This feature can be used to implement memory partitioning
and to eliminate address conflicts between system bus
devices and resident bus devices.
4-336

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84069012A 전자부품, 판매, 대치품
Timing Waveforms (Note 3)
STATE
T4
CLK
TCHSV
(5)
S2, S1, S0
T1
TCLCL
(1)
TSVCH
(4)
82C88
T2
TCLCH
(2)
TCHCL
(3)
T3
TCLSH
(7)
T4
TSHCL
(6)
ADDRESS/DATA
ALE
TCLLH
(10)
ADDRESS
VALID
TCHLL (14)
TSVLH (12)
2
WRITE 1
DATA VALID
MRDC, IORC, INTA,
AMWC, AIOWC
TCLML
(15)
TCLML
(15)
TCLMH
(16)
MWTC, IOWC
DEN (READ)
(INTA)
PDEN (READ)
(INTA)
DEN (WRITE)
TCVNV
(8)
TCVNV
(8)
TCVNX
(9)
PDEN (WRITE)
TCHDTH
(18)
TCVNX
(9)
DT/R (READ)
(INTA)
MCE
TCHDTL
(17)
2
TCHDTH
(18)
NOTES:
TCLMCH
(11)
TSVMCH
(13)
TCVNX
(9)
1. Address/Data Bus is shown only for reference purposes.
2. Leading edge of ALE and MCE is determined by the falling edge of CLK or status going active. Whichever occurs last.
3. All timing measurements are made at 1.5V unless otherwise specified.
FIGURE 1.
4-339

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부품번호상세설명 및 기능제조사
84069012A

CMOS Bus Controller

Intersil Corporation
Intersil Corporation

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