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8600V 데이터시트 PDF




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부품번호 8600V 기능
기능 3.3V In-System Programmable SuperBIG High Density PLD
제조업체 Lattice Semiconductor
로고 Lattice Semiconductor 로고


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8600V 데이터시트, 핀배열, 회로
ispLSI® 8600V
3.3V In-System Programmable
SuperBIG™ High Density PLD
Features
• SuperBIG HIGH DENSITY IN-SYSTEM
PROGRAMMABLE LOGIC
— 3.3V Power Supply
— 32,000 PLD Gates/600 Macrocells
— 192-264 I/O Pins Supporting 3.3V/2.5V I/O
— 864 Registers
— High-Speed Global and Big Fast Megablock (BFM)
Interconnect
— Wide 20-Macrocell Generic Logic Block (GLB) for
High Performance
— Wide Input Gating (44 Inputs per GLB) for Fast
Counters, State Machines, Address Decoders, Etc.
— PCB-Efficient Ball Grid Array (BGA) Package
Options
• HIGH-PERFORMANCE E2CMOS® TECHNOLOGY
fmax = 125 MHz Maximum Operating Frequency
tpd = 8.5 ns Propagation Delay
— Electrically Erasable and Reprogrammable
— Non-Volatile
— Programmable Speed/Power Logic Path
Optimization
• IN-SYSTEM PROGRAMMABLE
— Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
— Reprogram Soldered Devices for Faster Debugging
• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE AND
3.3V IN-SYSTEM PROGRAMMABLE
• ARCHITECTURE FEATURES
— Enhanced Pin-Locking Architecture, Symmetrical
Generic Logic Blocks Connected by Hierarchical
Big Fast Megablock and Global Routing Planes
— Product Term Sharing Array Supports up to 28
Product Terms per Macrocell Output
— Macrocells Support Concurrent Combinatorial and
Registered Functions
— Embedded Tristate Bus Can Be Used as an Internal
Tristate Bus or as an Extension of an External
Tristate Bus
— Macrocell and I/O Registers Feature Multiple Control
Options, Including Set, Reset and Clock Enable
— I/O Pins Support Programmable Bus Hold, Pull-Up,
Open-Drain and Slew Rate Options
— Separate VCCIO Power Supply to Support 3.3V or
2.5V Input/Output Logic Levels
— I/O Cell Register Programmable as Input Register for
Fast Setup Time or Output Register for Fast Clock to
Output Time
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER™
— PC and UNIX Platforms
Functional Block Diagram
12 12 12 12 12 12
I/O I/O I/O I/O I/O I/O
12
I/O
Big Fast Megablock 0
12
I/O
12
I/O
Big Fast Megablock 1
12
I/O
12
I/O
Big Fast Megablock 2
Global Routing Plane
12
I/O
Big Fast Megablock 3
12
I/O
12
I/O
12
I/O
Big Fast Megablock 4
12
I/O
Boundary
Scan
12 12 12 12 12 12
I/O I/O I/O I/O I/O I/O
8600v block
ispLSI 8000V Family Description
The ispLSI 8000V Family of Register-Intensive, 3.3V
SuperBIG In-System Programmable Logic Devices is
based on Big Fast Megablocks of 120 registered macro-
cells and a Global Routing Plane (GRP) structure
interconnecting the Big Fast Megablocks. Each Big Fast
Megablock contains 120 registered macrocells arranged
in six groups of 20, a group of 20 being referred to as a
Generic Logic Block, or GLB. Within the Big Fast
Megablock, a Big Fast Megablock Routing Pool (BRP)
interconnects the six GLBs to each other and to 24 Big
Fast Megablock I/O cells with optional I/O registers. The
Global Routing Plane which interconnects the Big Fast
Megablocks has additional global I/Os with optional I/O
registers. The 192-I/O version contains 72 Big Fast
Megablock I/O and 120 global I/O, while the 264-I/O
Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
July 2000
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
8600v_03
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8600V pdf, 반도체, 판매, 대치품
Specifications ispLSI 8600V
ispLSI 8000V Family Description (Continued) Embedded Tristate Bus
powered from 3.3V. The output drivers also provide
individually programmable edge rates and open drain
capability. A programmable pullup resistor is provided to
tie off unused inputs and a programmable bus-hold latch
is available to hold tristate outputs in their last valid state
until the bus is driven again by another device.
The ispLSI 8000V Family features 3.3V, non-volatile in-
system programmability for both the logic and the
interconnect structures, providing the means to develop
truly reconfigurable systems. Programming is achieved
through the industry standard IEEE 1149.1-compliant
Boundary Scan interface using the JTAG protocol. Bound-
ary Scan test is also supported through the same interface.
An enhanced, multiple cell security scheme is provided
that prevents reading of the JEDEC programming file
when secured. After the device has been secured using
this mechanism, the only way to clear the security is to
execute a bulk-erase instruction.
ispLSI 8600V Description
The ispLSI 8600V device has five Big Fast Megablocks
for a total of 5 x 120 = 600 macrocells.
Each Big Fast Megablock has a total of 24 I/O cells and
the Global Routing Plane has a total of 144 I/O cells. This
gives (5 x 24) + 144 = 264 I/Os for the full I/O version,
while the partial I/O version contains 72 BFM I/O + 120
Global I/O = 192 I/Os.
The total registers in the device is the sum of macrocells
plus I/O cells, 600 + 264 = 864 registers.
There is a 108-line embedded internal tristate bus as part
of the Global Routing Plane (GRP), enabling multiple
GLBs to drive the same tracks. This bus can be parti-
tioned into various bus widths such as twelve 9-line
buses, six 18-line buses or three 36-line buses. The
GLBs can dynamically share a subset of the Global
Routing Plane tracks. This feature eliminates the need to
convert tristate buses to wide multiplexers on the pro-
grammable device. Up to 18 macrocells per GLB can
participate in driving the embedded tristate bus. The
remaining two macrocells per GLB are used to generate
the internal tristate driver control signals on each data
byte (with parity). The embedded tristate bus can also be
configured as an extension of an external tristate bus
using the bidirectional capability of the I/O cells con-
nected to the Global Routing Plane. The Global Routing
Plane I/Os 0-8 and 15-23 from each group (I/OGx as
defined in the I/O Pin Location Table) can connect to the
internal tristate bus as well as the unidirectional/non-
tristate global routing channels. I/Os 9-14 connect only to
the global routing channel.
The embedded tristate bus has internal bus hold and
arbitration features in order to make the function more
“user friendly”. The bus hold feature keeps the internal
bus at the previously driven logic state when the bus is
not driven to eliminate bus float. The bus arbitration is
performed on a “first come, first served” priority. In other
words, once a logic block drives the bus, other logic
blocks cannot drive the bus until the first releases the bus.
This arbitration feature prevents internal bus contention
when there is an overlap between two bus enable sig-
nals. Typically, it takes about 3ns to resolve one bus
signal coming off the bus to another bus signal driving the
bus. The arbitration feature, combined with the predict-
ability of the CPLD, makes the embedded tristate bus the
most practical for real world bus implementation.
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8600V 전자부품, 판매, 대치품
Figure 4. ispLSI 8000V I/O Cell
TOE
GLOBAL OE0
GLOBAL OE1
GLOBAL OE2
GLOBAL OE3
From Output
Control Bus
Multiplexed Output From
Big Fast Megablock or
Global Track
GLOBAL I/O CLOCK ENABLE
From Output
Control Bus
GLOBAL CLOCK0
GLOBAL CLOCK2
QUADRANT I/O CLOCK
From Output
Control Bus
GRST
From Output
Control Bus
Specifications ispLSI 8600V
VCCIO VCCIO
VCCIO
DQ
CLKEN
R/L
PR
Slew Open
Rate Drain
Big Fast Megablock I/O Pad
or Global I/O Pad
To Specific
Big Fast Megablock
or Global Tracks
To Specific
Global Tristate Bus
From Output
Control Bus
Global I/O Cell
Only
: Function Selector (E2 Cell Controlled)
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부품번호상세설명 및 기능제조사
8600V

3.3V In-System Programmable SuperBIG High Density PLD

Lattice Semiconductor
Lattice Semiconductor

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