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기능 TMOS POWER FET 1.5 AMPERES 60 VOLT
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MMFT3055VL 데이터시트, 핀배열, 회로
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MMFT3055VL/D
Designer's Data Sheet
TMOS V
SOT-223 for Surface Mount
MMFT3055VL
N–Channel Enhancement–Mode Silicon Gate
TMOS V is a new technology designed to achieve an on–resis-
tance area product about one–half that of standard MOSFETs. This
new technology more than doubles the present cell density of our
50 and 60 volt TMOS devices. Just as with our TMOS E–FET
designs, TMOS V is designed to withstand high energy in the
avalanche and commutation modes. Designed for low voltage, high
speed switching applications in power supplies, converters and
power motor controls, these devices are particularly well suited for
bridge circuits where diode speed and commutating safe operating
areas are critical and offer additional safety margin against
unexpected voltage transients.
New Features of TMOS V
On–resistance Area Product about One–half that of Standard
MOSFETs with New Low Voltage, Low RDS(on) Technology
Faster Switching than E–FET Predecessors
G
TM
D
S
TMOS POWER FET
1.5 AMPERES
60 VOLTS
RDS(on) = 0.140 OHM
1
2
3
4
CASE 318E–04, Style 3
TO–261AA
Features Common to TMOS V and TMOS E–FETS
Avalanche Energy Specified
IDSS and VDS(on) Specified at Elevated Temperature
Static Parameters are the Same for both TMOS V and TMOS E–FET
Available in 12 mm Tape & Reel
Use MMFT3055VLT1 to order the 7 inch/1000 unit reel
Use MMFT3055VLT3 to order the 13 inch/4000 unit reel
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain–to–Source Voltage
Drain–to–Gate Voltage (RGS = 1.0 M)
Gate–to–Source Voltage – Continuous
Gate–to–Source Voltage – Non–repetitive (tp 10 ms)
Drain Current – Continuous
Drain Current – Continuous @ 100°C
Drain Current – Single Pulse (tp 10 µs)
Total PD @ TA = 25°C mounted on 1” sq. Drain pad on FR–4 bd material
Total PD @ TA = 25°C mounted on 0.70” sq. Drain pad on FR–4 bd material
Total PD @ TA = 25°C mounted on min. Drain pad on FR–4 bd material
Derate above 25°C
VDSS
VDGR
VGS
VGSM
ID
ID
IDM
PD
60
60
± 15
± 20
1.5
1.2
5.0
2.1
1.7
0.94
6.3
Vdc
Vdc
Vdc
Vpk
Adc
Apk
Watts
mW/°C
Operating and Storage Temperature Range
Single Pulse Drain–to–Source Avalanche Energy – Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 5.0 Vdc, Peak IL = 3.4 Apk, L = 10 mH, RG = 25 )
Thermal Resistance
– Junction to Ambient on 1” sq. Drain pad on FR–4 bd material
– Junction to Ambient on 0.70” sq. Drain pad on FR–4 bd material
– Junction to Ambient on min. Drain pad on FR–4 bd material
Maximum Lead Temperature for Soldering Purposes, 1/8from case for 10 seconds
TJ, Tstg
EAS
– 55 to 175
58
RθJA
RθJA
RθJA
TL
70
88
159
260
°C
mJ
°C/W
°C
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET, Designer’s, and TMOS V are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
REV 1
© MMoototororloa,laIncT.M19O96S Power MOSFET Transistor Device Data
1




MMFT3055VL pdf, 반도체, 판매, 대치품
MMFT3055VL
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are deter-
mined by how fast the FET input capacitance can be charged
by current from the generator.
The published capacitance data is difficult to use for calculat-
ing rise and fall because drain–gate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a resis-
tive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG – VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate val-
ues from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG – VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off–state condition when cal-
culating td(on) and is read at a voltage corresponding to the
on–state when calculating td(off).
At high switching speeds, parasitic circuit elements com-
plicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a func-
tion of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to mea-
sure and, consequently, is not specified.
The resistive switching time variation versus gate resis-
tance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely op-
erated into an inductive load; however, snubbing reduces
switching losses.
1000
VDS = 0 V VGS = 0 V
900
TJ = 25°C
800 Ciss
700
600 Crss
500
400 Ciss
300
200
100
0
10
505
VGS VDS
Coss
Crss
10 15 20 25
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
4 Motorola TMOS Power MOSFET Transistor Device Data

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MMFT3055VL 전자부품, 판매, 대치품
MMFT3055VL
INFORMATION FOR USING THE SOT–223 SURFACE MOUNT PACKAGE
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the total
design. The footprint for the semiconductor packages must be
the correct size to insure proper solder connection interface
between the board and the package. With the correct pad
geometry, the packages will self align when subjected to a
solder reflow process.
0.15
3.8
0.079
2.0
0.091
2.3
0.091
2.3
0.079
2.0
0.059
1.5
0.059
1.5
0.059
1.5
SOT–223
0.248
6.3
inches
mm
SOT–223 POWER DISSIPATION
The power dissipation of the SOT–223 is a function of the
drain pad size. This can vary from the minimum pad size for
soldering to a pad size given for maximum power dissipation.
Power dissipation for a surface mount device is determined by
TJ(max), the maximum rated junction temperature of the die,
RθJA, the thermal resistance from the device junction to
ambient, and the operating temperature, TA. Using the values
provided on the data sheet for the SOT–223 package, PD can
be calculated as follows:
dissipation can be increased. Although one can almost double
the power dissipation with this method, one will be giving up
area on the printed circuit board which can defeat the purpose
of using surface mount technology. A graph of RθJA versus
drain pad area is shown in Figure 17.
160
Board Material = 0.0625
140 G–10/FR–4, 2 oz Copper
TA = 25°C
PD =
TJ(max) – TA
RθJA
°
120
0.8 Watts
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values into
the equation for an ambient temperature TA of 25°C, one can
calculate the power dissipation of the device which in this case
is 943 milliwatts.
PD = 175°C – 25°C = 943 milliwatts
159°C/W
The 159°C/W for the SOT–223 package assumes the use
of the recommended footprint on a glass epoxy printed circuit
board to achieve a power dissipation of 943 milliwatts. There
are other alternatives to achieving higher power dissipation
from the SOT–223 package. One is to increase the area of the
drain pad. By increasing the area of the drain pad, the power
1.25 Watts*
1.5 Watts
100
*Mounted on the DPAK footprint
80
0.0 0.2 0.4
0.6
A, Area (square inches)
0.8
1.0
Figure 15. Thermal Resistance versus Drain Pad
Area for the SOT–223 Package (Typical)
Another alternative would be to use a ceramic substrate or
an aluminum core board such as Thermal Clad. Using a
board material such as Thermal Clad, an aluminum core
board, the power dissipation can be doubled using the same
footprint.
Motorola TMOS Power MOSFET Transistor Device Data
7

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