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PDF MMFT5P03HD Data sheet ( Hoja de datos )
| Número de pieza | MMFT5P03HD | |
| Descripción | TMOS MEDIUM POWER FET 5.2 AMPERES 30 VOLTS | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MMFT5P03HD/D
™Designer's Data Sheet
Medium Power Surface Mount Products
TMOS P-Channel
MMFT5P03HD
Motorola Preferred Device
Field Effect Transistor
MMFT5P03HD is an advanced power MOSFET which utilizes
Motorola’s High Cell Density HDTMOS process. This miniature
surface mount MOSFET features ultra low RDS(on) and true logic
level performance. It is capable of withstanding high energy in the
™
avalanche and commutation modes and the drain–to–source diode
has a very low reverse recovery time. MMFT5P03HD devices are
designed for use in low voltage, high speed switching applications
where power efficiency is important. Typical applications are dc–dc
2, 4
D
converters, and power management in portable and battery
powered products such as computers, printers, cellular and
cordless phones. They can also be used for low voltage motor
controls in mass storage products such as disk drives and tape
drives. The avalanche energy is specified to eliminate the
guesswork in designs where inductive loads are switched and offer
G
1
additional safety margin against unexpected voltage transients.
S
• Ultra Low RDS(on) Provides Higher Efficiency and Extends
3
Battery Life
• Logic Level Gate Drive — Can Be Driven by Logic ICs
• Miniature SOT–223 Surface Mount Package — Saves Board
Space
• Diode Is Characterized for Use In Bridge Circuits
• Diode Exhibits High Speed, With Soft Recovery
• IDSS Specified at Elevated Temperature
• Avalanche Energy Specified
TMOS MEDIUM
POWER FET
5.2 AMPERES
30 VOLTS
RDS(on) = 100 mΩ
4
1
23
CASE 318E–04, Style 3
TO–261AA
DEVICE MARKING
ORDERING INFORMATION
5P03H
Device
MMFT5P03HDT3
Reel Size
13″
Tape Width
12 mm embossed tape
Quantity
4000 units
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
Preferred devices are Motorola recommended choices for future use and best overall value.
HDTMOS is a trademark of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc. Micro8 is a registered trademark of International
Rectifier. Thermal Clad is a trademark of the Bergquist Company.
REV 2
©MMoottoororolal,aInTc.M19O9S7 Power MOSFET Transistor Device Data
1
1 page  
POWER MOSFET SWITCHING
MMFT5P03HD
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (∆t) are deter-
mined by how fast the FET input capacitance can be charged
by current from the generator.
The published capacitance data is difficult to use for calculat-
ing rise and fall because drain–gate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a resis-
tive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG – VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate val-
ues from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG – VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off–state condition when cal-
culating td(on) and is read at a voltage corresponding to the
on–state when calculating td(off).
At high switching speeds, parasitic circuit elements com-
plicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a func-
tion of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to mea-
sure and, consequently, is not specified.
The resistive switching time variation versus gate resis-
tance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely op-
erated into an inductive load; however, snubbing reduces
switching losses.
1500 VDS = 0 V
Ciss
1200
VGS = 0 V
900 Crss
TJ = 25°C
600
300
0
–10
Ciss
Coss
Crss
0
VGS VDS
10
20
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
30
Motorola TMOS Power MOSFET Transistor Device Data
5
5 Page 
PACKAGE DIMENSIONS
MMFT5P03HD
A
F
4
S
1 23
B
STYLE 3:
PIN 1.
2.
3.
4.
GATE
DRAIN
SOURCE
DRAIN
L
G
0.08 (0003)
H
D
C
M
J
K
CASE 318E–04
ISSUE H
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
INCHES
DIM MIN MAX
A 0.249 0.263
B 0.130 0.145
C 0.060 0.068
D 0.024 0.035
F 0.115 0.126
G 0.087 0.094
H 0.0008 0.0040
J 0.009 0.014
K 0.060 0.078
L 0.033 0.041
M 0_ 10 _
S 0.264 0.287
MILLIMETERS
MIN MAX
6.30 6.70
3.30 3.70
1.50 1.75
0.60 0.89
2.90 3.20
2.20 2.40
0.020 0.100
0.24 0.35
1.50 2.00
0.85
0_
6.70
1.05
10 _
7.30
Motorola TMOS Power MOSFET Transistor Device Data
11
11 Page | ||
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| PDF Descargar | [ Datasheet MMFT5P03HD.PDF ] | |
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