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기능 SINGLE TMOS POWER MOSFET 10 AMPERES 20 VOLTS
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MMSF10N02Z 데이터시트, 핀배열, 회로
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MMSF10N02Z/D
Designer's Data Sheet
Medium Power Surface Mount Products
TMOS Single N-Channel with
Monolithic Zener ESD
Protected Gate
EZFETsare an advanced series of power MOSFETs which
utilize Motorola’s High Cell Density HDTMOS process and contain
monolithic back–to–back zener diodes. These zener diodes
provide protection against ESD and unexpected transients. These
miniature surface mount MOSFETs feature low RDS(on) and true
logic level performance. They are capable of withstanding high
energy in the avalanche and commutation modes and the
drain–to–source diode has a very low reverse recovery time.
EZFET devices are designed for use in low voltage, high speed
switching applications where power efficiency is important.
Zener Protected Gates Provide Electrostatic Discharge Protection
Low RDS(on) Provides Higher Efficiency and Extends Battery Life
Logic Level Gate Drive — Can Be Driven by Logic ICs
Miniature SO–8 Surface Mount Package — Saves Board Space
Diode Exhibits High Speed, With Soft Recovery
IDSS Specified at Elevated Temperature
Mounting Information for SO–8 Package Provided
G
MMSF10N02Z
Motorola Preferred Device
SINGLE TMOS
POWER MOSFET
10 AMPERES
20 VOLTS
RDS(on) = 0.015 OHM
D
S
CASE 751–05, Style 12
SO–8
Source
Source
Source
Gate
18
27
36
45
Top View
Drain
Drain
Drain
Drain
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Drain–to–Source Voltage
Drain–to–Gate Voltage (RGS = 1.0 M)
Gate–to–Source Voltage — Continuous
Drain Current — Continuous @ TA = 25°C
Drain Current — Continuous @ TA = 70°C
Drain Current — Single Pulse (tp 10 µs)
Total Power Dissipation @ TA = 25°C (1)
Operating and Storage Temperature Range
Thermal Resistance — Junction to Ambient
Maximum Temperature for Soldering
(1) When mounted on 1 inch square FR–4 or G–10 board (VGS = 4.5 V, @ 10 Seconds)
Symbol
VDSS
VDGR
VGS
ID
ID
IDM
PD
TJ, Tstg
RθJA
TL
Value
20
20
± 12
10
7.0
80
2.5
– 55 to 150
50
260
Unit
Vdc
Vdc
Vdc
Adc
Apk
Watts
°C
°C/W
°C
DEVICE MARKING
ORDERING INFORMATION
10N02Z
Device
MMSF10N02ZR2
Reel Size
13
Tape Width
12 mm embossed tape
Quantity
2500 units
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
Preferred devices are Motorola recommended choices for future use and best overall value.
Designer’s, HDTMOS and EZFET are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc. Thermal Clad is a trade-
mark of the Bergquist Company.
REV 2
©MMoottoororolal,aInTc.M19O9S7 Power MOSFET Transistor Device Data
1




MMSF10N02Z pdf, 반도체, 판매, 대치품
MMSF10N02Z
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are deter-
mined by how fast the FET input capacitance can be charged
by current from the generator.
The published capacitance data is difficult to use for calculat-
ing rise and fall because drain–gate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a resis-
tive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG – VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate val-
ues from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG – VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off–state condition when cal-
culating td(on) and is read at a voltage corresponding to the
on–state when calculating td(off).
At high switching speeds, parasitic circuit elements com-
plicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a func-
tion of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to mea-
sure and, consequently, is not specified.
The resistive switching time variation versus gate resis-
tance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely op-
erated into an inductive load; however, snubbing reduces
switching losses.
2000
TJ = 25°C
VGS = 0 V
1500
Ciss
1000
Coss
500 Crss
0
0 2 4 6 8 10 12 14 16 18 20
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
4 Motorola TMOS Power MOSFET Transistor Device Data

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MMSF10N02Z 전자부품, 판매, 대치품
1
D = 0.5
0.2
0.1
0.1
0.05
0.02
0.01
0.01
TYPICAL ELECTRICAL CHARACTERISTICS
MMSF10N02Z
0.001
1.0E–05
SINGLE PULSE
1.0E–04
1.0E–03
1.0E–02
1.0E–01
1.0E+00
t, TIME (s)
Figure 13. Thermal Response
1.0E+01
1.0E+02
1.0E+03
IS
tp
di/dt
trr
ta tb
0.25 IS
IS
TIME
Figure 14. Diode Reverse Recovery Waveform
Motorola TMOS Power MOSFET Transistor Device Data
7

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MMSF10N02Z

SINGLE TMOS POWER MOSFET 10 AMPERES 20 VOLTS

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MMSF10N02Z

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