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부품번호 MMSF10N03Z 기능
기능 SINGLE TMOS POWER MOSFET 10 AMPERES 30 VOLTS
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MMSF10N03Z 데이터시트, 핀배열, 회로
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MMSF10N03Z/D
Advance Information
Medium Power Surface Mount Products
TMOS Single N-Channel with
MMSF10N03Z
Motorola Preferred Device
Monolithic Zener ESD Protected Gate
EZFETsare an advanced series of power MOSFETs which utilize
Motorola’s High Cell Density TMOS process and contain monolithic
back–to–back zener diodes. These zener diodes provide protection
against ESD and unexpected transients. These miniature surface mount
MOSFETs feature ultra low RDS(on) and true logic level performance. They
are capable of withstanding high energy in the avalanche and commuta-
tion modes and the drain–to–source diode has a very low reverse recovery
time. EZFET devices are designed for use in low voltage, high speed
switching applications where power efficiency is important. Typical
applications are dc–dc converters, and power management in portable
and battery powered products such as computers, printers, cellular and
cordless phones. They can also be used for low voltage motor controls in
mass storage products such as disk drives and tape drives.
Zener Protected Gates Provide Electrostatic Discharge Protection
Designed to Withstand 200 V Machine Model and 2000 V Human Body Model D
Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life
Logic Level Gate Drive — Can Be Driven by Logic ICs
Miniature SO–8 Surface Mount Package — Saves Board Space
Diode Is Characterized for Use In Bridge Circuits
G
Diode Exhibits High Speed, With Soft Recovery
IDSS Specified at Elevated Temperature
Mounting Information for SO–8 Package Provided
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Parameter
S
SINGLE TMOS
POWER MOSFET
10 AMPERES
30 VOLTS
RDS(on) = 13 mW
CASE 751–05, Style 12
SO–8
Source
Source
Source
Gate
18
27
36
45
Top View
Drain
Drain
Drain
Drain
Symbol
Max
Unit
Drain–to–Source Voltage
Drain–to–Gate Voltage (RGS = 1.0 M)
Gate–to–Source Voltage — Continuous
Drain Current — Continuous @ TA = 25°C (1)
Drain Current — Continuous @ TA = 70°C (1)
Drain Current — Pulsed Drain Current (3)
Total Power Dissipation @ TA = 25°C (1)
Linear Derating Factor @ TA = 25°C (1)
Total Power Dissipation @ TA = 25°C (2)
Linear Derating Factor @ TA = 25°C (2)
Operating and Storage Temperature Range
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
W(VDD = 30 Vdc, VGS = 10 Vdc, IL = 10 Apk, L = 20 mH, RG = 25 )
THERMAL RESISTANCE
VDSS
VDGR
VGS
ID
ID
IDM
PD
PD
TJ, Tstg
EAS
30
30
± 20
10
7.7
50
2.5
20
1.6
12
– 55 to 150
1000
Vdc
Vdc
Vdc
Adc
Watts
mW/°C
Watts
mW/°C
°C
mJ
Junction–to–Ambient (1)
Junction–to–Ambient (2)
Parameter
Symbol
RqJA
(1) When mounted on 1” square FR4 or G–10 board (VGS = 10 V, @ 10 seconds).
(2) When mounted on minimum recommended FR4 or G–10 board (VGS = 10 V, @ Steady State).
(3) Repetitive rating; pulse width limited by maximum junction temperature.
DEVICE MARKING
ORDERING INFORMATION
Typ
Max Unit
50 °C/W
80
S10N3Z
Device
MMSF10N03ZR2
Reel Size
13
Tape Width
12 mm embossed tape
This document contains information on a new product. Specifications and information herein are subject to change without notice.
HDTMOS is a trademark of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
Preferred devices are Motorola recommended choices for future use and best overall value.
Quantity
2500 units
©MMoottoororolal,aInTc.M19O9S7 Power MOSFET Transistor Device Data
1




MMSF10N03Z pdf, 반도체, 판매, 대치품
MMSF10N03Z
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (t) are deter-
mined by how fast the FET input capacitance can be charged
by current from the generator.
The published capacitance data is difficult to use for calculat-
ing rise and fall because drain–gate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a resis-
tive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG – VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate val-
ues from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG – VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off–state condition when cal-
culating td(on) and is read at a voltage corresponding to the
on–state when calculating td(off).
At high switching speeds, parasitic circuit elements com-
plicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a func-
tion of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to mea-
sure and, consequently, is not specified.
The resistive switching time variation versus gate resis-
tance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely op-
erated into an inductive load; however, snubbing reduces
switching losses.
5000
VDS = 0 V VGS = 0 V
4000 Ciss
TJ = 25°C
3000
2000
Crss
1000
0
–10 –5.0
Ciss
Coss
Crss
0 5.0 10 15
20
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
4 Motorola TMOS Power MOSFET Transistor Device Data

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MMSF10N03Z 전자부품, 판매, 대치품
1
D = 0.5
0.2
0.1
0.1
0.05
0.02
0.01
0.01
SINGLE PULSE
0.001
1.0E–05
1.0E–04
TYPICAL ELECTRICAL CHARACTERISTICS
MMSF10N03Z
1.0E–03
P(pk)
t1
t2
DUTY CYCLE, D = t1/t2
RθJC(t) = r(t) RθJC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) – TC = P(pk) RθJC(t)
1.0E–02
1.0E–01
t, TIME (s)
1.0E+00
1.0E+01
1.0E+02
1.0E+03
Figure 14. Thermal Response
IS
tp
di/dt
trr
ta tb
0.25 IS
IS
TIME
Figure 15. Diode Reverse Recovery Waveform
Motorola TMOS Power MOSFET Transistor Device Data
7

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SINGLE TMOS POWER MOSFET 10 AMPERES 30 VOLTS

Motorola Semiconductors
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