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PDF 87C453 Data sheet ( Hoja de datos )
| Número de pieza | 87C453 | |
| Descripción | 80C51 8-bit microcontroller family 8K/256 OTP/ROM/ expanded I/O | |
| Fabricantes | NXP Semiconductors | |
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INTEGRATED CIRCUITS
83C453/87C453
80C51 8-bit microcontroller family
8K/256 OTP/ROM, expanded I/O
Preliminary specification
Supersedes data of 1997 Dec 29
IC20 Data Handbook
1998 Apr 23
Philips
Semiconductors
1 page  
Philips Semiconductors
80C51 8-bit microcontroller family
8K/256 OTP/ROM, expanded I/O
Preliminary specification
83C453/87C453
PIN DESCRIPTION
MNEMONIC
VSS
VCC
P0.0–0.7
PIN NO.
54
18
17-10
P1.0–P1.7
27-34
P2.0–P2.7
2-9
P3.0–P3.7
36-43
P4.0–P4.3
P4.0–P4.7
P5.0–P5.7
P6.0–P6.7
36
37
38
39
40
41
42
43
26-19
44-51
59-66
ODS
IDS
BFLAG
AFLAG
RST
ALE/PROG
55
56
57
58
35
68
PSEN
67
EA/VPP
XTAL1
XTAL2
1
53
52
TYPE NAME AND FUNCTION
I Ground: 0V reference.
I Power Supply: This is the power supply voltage for normal, idle, and power-down operation.
I/O Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 is also the multiplexed data and low-order
address bus during accesses to external memory. External pull-ups are required during program
verification. Port 0 can sink/source eight LS TTL inputs.
I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 receives the low-order address
bytes during program memory verification. Port 1 can sink/source three LS TTL inputs, and drive CMOS
inputs without external pull-ups.
I/O Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 emits the high-order address
bytes during access to external memory and receives the high-order address bits and control signals
during program verification. Port 2 can sink/source three LS TTL inputs, and drive CMOS inputs without
external pull-ups.
I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 can sink/source three LS TTL
inputs, and drive CMOS inputs without external pull-ups. Port 3 also serves the special functions listed
below:
I RxD (P3.0): Serial input port
O TxD (P3.1): Serial output port
I INT0 (P3.2): External interrupt
I INT1 (P3.3): External interrupt
I T0 (P3.4): Timer 0 external input
I T1 (P3.5): Timer 1 external input
O WR (P3.6): External data memory write strobe
O RD (P3.7): External data memory read strobe
I/O Port 4: Port 4 is an 8-bit bidirectional I/O port with internal pull-ups. Port 4 can sink/source three LS TTL
I/O inputs and drive CMOS inputs without external pull-ups.
I/O Port 5: Port 5 is an 8-bit bidirectional I/O port with internal pull-ups. Port 5 can sink/source three LS TTL
inputs and drive CMOS inputs without external pull-ups.
I/O Port 6: Port 6 is a specialized 8-bit bidirectional I/O port with internal pull-ups. This special port can
sink/source three LS TTL inputs and drive CMOS inputs without external pull-ups. Port 6 can be used in a
strobed or non-strobed mode of operation. Port 6 works in conjunction with four control pins that serve the
functions listed below:
I ODS: Output data strobe
I IDS: Input data strobe
I/O BFLAG: Bidirectional I/O pin with internal pull-ups
I/O AFLAG: Bidirectional I/O pin with internal pull-ups
I Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An
internal pull-down resistor permits a power-on reset using only an external capacitor connected to VCC.
I/O Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the address during an
access to external memory. ALE is activated at a constant rate of 1/6 the oscillator frequency except during
an external data memory access, at which time one ALE is skipped. ALE can sink/source three LS TTL
inputs and drive CMOS inputs without external pull-ups. This pin is also the program pulse during EPROM
programming.
O Program Store Enable: The read strobe to external program memory. PSEN is activated twice each
machine cycle during fetches from external program memory. However, when executing out of external
program memory, two activations of PSEN are skipped during each access to external program memory.
PSEN is not activated during fetches from internal program memory. PSEN can sink/source eight LS TTL
inputs and drive CMOS inputs without an external pull-up. This pin should be tied low during programming.
I Instruction Execution Control/Programming Supply Voltage: When EA is held high, the CPU executes
out of internal program memory, unless the program counter exceeds 1FFFH. When EA is held low, the
CPU executes out of external program memory. EA must never be allowed to float. This pin also receives
the 12.75V programming supply voltage (VPP) during EPROM programming.
I Crystal 1: Input to the inverting oscillator amplifier that forms the oscillator. This input receives the external
oscillator when an external oscillator is used.
O Crystal 2: An output of the inverting amplifier that forms the oscillator. This pin should be floated when an
external oscillator is used.
1998 Apr 23
5
5 Page 
Philips Semiconductors
80C51 8-bit microcontroller family
8K/256 OTP/ROM, expanded I/O
Preliminary specification
83C453/87C453
In the above example the differentiation among the 3 slaves is in the
lower 3 address bits. Slave 0 requires that bit 0 = 0 and it can be
uniquely addressed by 1110 0110. Slave 1 requires that bit 1 = 0 and
it can be uniquely addressed by 1110 and 0101. Slave 2 requires
that bit 2 = 0 and its unique address is 1110 0011. To select Slaves 0
and 1 and exclude Slave 2 use address 1110 0100, since it is
necessary t make bit 2 = 1 to exclude slave 2.
The Broadcast Address for each slave is created by taking the
logical OR of SADDR and SADEN. Zeros in this result are teated as
don’t-cares. In most cases, interpreting the don’t-cares as ones, the
broadcast address will be FF hexadecimal.
Upon reset SADDR (SFR address 0A9H) and SADEN (SFR
address 0B9H) are leaded with 0s. This produces a given address
of all “don’t cares” as well as a Broadcast address of all “don’t
cares”. this effectively disables the Automatic Addressing mode and
allows the microcontroller to use standard 80C51 type UART drivers
which do not make use of this feature.
The 87C453 UART has all of the capabilities of the standard 80C51
UART plus Framing Error Detection and Automatic Address
Recognition. As in the 80C51, all four modes of operation are
supported as well as the 9th bit in modes 2 and 3 that can be used
to facilitate multiprocessor communication.
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output, respectively, of an
inverting amplifier. The pins can be configured for use as an on-chip
oscillator.
To drive the device from an external clock source, XTAL1 should be
driven while XTAL2 is left unconnected. There are no requirements
on the duty cycle of the external clock signal, because the input to
the internal clock circuitry is through a divide-by-two flip-flop.
However, minimum and maximum high and low times specified in
the data sheet must be observed.
Reset
A reset is accomplished by holding the RST pin high for at least two
machine cycles (24 oscillator periods), while the oscillator is running.
To insure a good power-on reset, the RST pin must be high long
enough to allow the oscillator time to start up (normally a few
milliseconds) plus two machine cycles. At power-on, the voltage on
VCC and RST must come up at the same time for a proper start-up.
Idle Mode
In the idle mode, the CPU puts itself to sleep while all of the on-chip
peripherals stay active. The instruction to invoke the idle mode is the
last instruction executed in the normal operating mode before the
idle mode is activated. The CPU contents, the on-chip RAM, and all
of the special function registers remain intact during this mode. The
idle mode can be terminated either by any enabled interrupt (at
which time the process is picked up at the interrupt service routine
and continued), or by a hardware reset which starts the processor in
the same manner as a power-on reset.
Power-Down Mode
To save even more power, a Power Down mode can be invoked by
software. In this mode, the oscillator is stopped and the instruction
that invoked Power Down is the last instruction executed. The
on-chip RAM and Special Function Registers retain their values until
the Power Down mode is terminated.
On the 87C453 either a hardware reset or external interrupt can
cause an exit from Power Down. Reset redefines all the SFRs but
does not change the on-chip RAM. An external interrupt allows both
the SFRs and the on-chip RAM to retain their values.
To properly terminate Power Down the reset or external interrupt
should not be executed before VCC is restored to its normal
operating level and must be held active long enough for the
oscillator to restart and stabilize (normally less than 10ms).
With an external interrupt, INT0 and INT1 must be enabled and
configured as level-sensitive. Holding the pin low restarts the
oscillator but bringing the pin back high completes the exit. Once the
interrupt is serviced, the next instruction to be executed after RETI
will be the one following the instruction that put the device into
Power Down.
Power Off Flag
The Power Off Flag (POF) in PCON is set by on-chip circuitry when
the VCC level on the 87C453 rises from 0 to 5V. The POF bit can be
set or cleared by software allowing a user to determine if the reset is
the result of a power-on or a warm start after powerdown. The VCC
level must remain above 3V for the POF to remain unaffected by the
VCC level.
Design Consideration
• When the idle mode is terminated by a hardware reset, the device
normally resumes program execution, from where it left off, up to
two machine cycles before the internal rest algorithm takes
control. On-chip hardware inhibits access to internal RAM in this
event, but access to the port pins is not inhibited. To eliminate the
possibility of an unexpected write when Idle is terminated by reset,
the instruction following the one that invokes Idle should not be
one that writes to a port pin or to external memory.
ONCE™ Mode
The ONCE (“On-Circuit Emulation”) Mode facilitates testing and
debugging of systems using the 87C453 without having to remove
the IC from the circuit. The ONCE Mode is invoked by:
1. Pull ALE low while the device is in reset and PSEN is high;
2. Hold ALE low as RST is deactivated.
While the device is in ONCE Mode, the Port 0 pins go into a float
state, and the other port pins and ALE and PSEN are weakly pulled
high. The oscillator circuit remains active. While the 87C453 is in
this mode, an emulator or test CPU can be used to drive the circuit.
Normal operation is restored when a normal reset is applied.
PORTS 4 AND 5
Ports 4 and 5 are bidirectional I/O ports with internal pull-ups. Port 4
is an 8-bit port. Port 4 and port 5 pins with ones written to them, are
pulled high by the internal pull-ups, and in that state can be used as
inputs. Ports 4 and 5 are addressed at the special function register
addresses shown in Table 3.
PORT 6
Port 6 is a special 8-bit bidirectional I/O port with internal pull-ups
(see Figure 8). This port can be used as a standard I/O port, or in
strobed modes of operation in conjunction with four special control
lines: ODS, IDS, AFLAG, and BFLAG. Port 6 operating modes are
controlled by the port 6 control status register (CSR). Port 6 and the
CSR are addressed at the special function register addresses
shown in Table 3. The following four control pins are used in
conjunction with port 6:
ODS – Output data strobe for port 6. ODS can be programmed to
control the port 6 output drivers and the output buffer full flag (OBF),
or to clear only the OBF flag bit in the CSR (output-always mode).
1998 Apr 23
11
11 Page | ||
| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet 87C453.PDF ] | |
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