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PDF MXED102 Data sheet ( Hoja de datos )
| Número de pieza | MXED102 | |
| Descripción | 240-Channel OLED Column Driver | |
| Fabricantes | Clare. | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MXED102 (archivo pdf) en la parte inferior de esta página. Total 20 Páginas | ||
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MXED102
240-Channel OLED Column Driver
Features
• CMOS High Voltage Process: 9V-30V Display Panel
Supply Compatible
• 240 Output Channels, Cascadable
• Token-Based Bidirectional Data Transfer: Direct User
Control of Scan Rate
• Current Source Magnitude User Control: 4 µA to 1 mA
• 6-Bit Monochromatic/Color Gray-Scale User Control
• Current matching accuracy: ± 2% ± 1.5 µA intra-die
± 1% inter-die
• Monochromatic/Color Voltage Precharge Options
• Built-In A-to-D Converter Monitoring of Display Panel
Characteristics
• 3.3 V to 5 V logic supply
• Up to 35 MHz clock frequency
• Gold-Bumped Die @ 60 micron Output Pitch
• TCP packaging
• Companion to Clare Micronix MXED202
128-Channel OLED Row Driver
Description
The MXED102 is Clare’s second-generation OLED col-
umn driver offering, which supports up to 240-mono-
chromatic or 80-color OLED pixels. The MXED102's
exceptionally tight current-matching of adjacent and
cascaded outputs, precharge options, and OLED moni-
toring capability, ensures uniform luminance and high-
quality greyscaling in both monochromatic and RGB
mode. This is the first ASSP production driver for OLED
module OEM's building a new standard in flat-panel dis-
plays.
For All Passive-Matrix Organic-Light-Emitting-
Diode Displays
• Monochrome and Color
• Small-Molecule and Polymer
• Current-Sourcing Anode Drivers
Column Driver Block Diagram
DS-MXED102-R2
Preliminary
www.clare.com
1
1 page  
Preliminary
MXED102
Digital Inputs:
Parameter
Input low voltage
Input high voltage
Input current
Sym
VIL
VIH
II
Operating Condition
-
-
-
Min
-
VCC-0.5
-10
Typ
-
-
-
Max
0.5
-
10
Units
V
V
uA
Digital Outputs:
Parameter
Sym
Output low voltage VOL
Output high voltage VOH
Output rise/fall time TRF
Operating Condition
Iout = 100 uA
Iout = -100 uA
10 to 90 %, Cload=5 pF
Min
-
VCC-0.4
-
Typ
-
-
-
Max
0.4
-
2.0
Units
V
V
nS
Serial Configuration Bus:
Bus Operation:
The controller uses the serial bus to set the characteristics of all column driver ICs by writing to all column
driver ICs in parallel. During write, the controller writes the entire data packet. The controller can also inter
rogate a single column driver IC, who's MASTER pin is pulled high. Only 1 column driver IC on a given bus
can be designated as master. During read, the controller writes the preamble, start of frame delimiter, reg
ister address, and turn around bits. It then tri-states for the bus tri-state and data bits and reads the data.
Data Packet:
The data packet consists of:
- 14 bit preamble of all 1's
- 2 bit start of frame delimiter (SFD)
- 6 bit register address - MSB first
- 1 turn around bit (TA)
- 1 bus tristate (BT)
- 8 bit data packet - MSB first
Write => write data to all column driver ICs
Read => read data from master column driver IC
Data order => Preamble first, data last; MSB first, LSB last
R/W
write
read
Preamble
1111 1111 1111 11
1111 1111 1111 11
SFD
00
01
Reg Address
AAAA AA
AAAA AA
TA BT
00
0Z
Data
DDDD DDDD
DDDD DDDD
Rev. 2 www.clare.com
5
5 Page 
Preliminary
Load Data Pattern Timing
MXED102
Rev. 2 www.clare.com
11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet MXED102.PDF ] | |
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