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기능 80C51 8-bit microcontroller family 4K/256 OTP/ROM/ DAC/ comparator/ UART/ reference
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87C754 데이터시트, 핀배열, 회로
INTEGRATED CIRCUITS
83C754/87C754
80C51 8-bit microcontroller family
4K/256 OTP/ROM, DAC, comparator, UART, reference
Preliminary specification
Supersedes data of 1997 Dec 03
IC20 Data Handbook
1998 Apr 23
Philips
Semiconductors




87C754 pdf, 반도체, 판매, 대치품
Philips Semiconductors
80C51 8-bit microcontroller family
4K/256 OTP/ROM, DAC, comparator, UART, reference
Preliminary specification
83C754/87C754
PIN DESCRIPTION
MNEMONIC
DIP TYPE
PIN NO.
NAME AND FUNCTION
VSS
VCC
P1.0–P1.2
P3.0–P3.7
8 I Circuit Ground Potential.
22 I Supply voltage during normal, idle, and power-down operation.
21, 23, 24 I/O Port 1: Port 1 is a 3-bit bidirectional I/O port with internal pull-ups on P1.0 and P1.1. Port 1 pins that
have 1s written to them can be used as inputs. As inputs, port 1 pins that are externally pulled low will
source current because of the internal pull-ups (P1.0, P1.1). (See DC Electrical Characteristics: IIL).
Port 1 also serves the special function features listed below (Note: P1.0 does not have the strong
pullup that is on for 2 oscillator periods.):
24 I INT0 (P1.0): External interrupt 0.
23 O CEX (P1.1): PCA clock output.
21 I VPP (P1.2): Programming voltage input (open drain).
1–4,
25–28
I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to
them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins that are
externally being pulled low will source current because of the pull-ups. (See DC Electrical
Characteristics: IIL). Port 3 also functions as the data input for the EPROM memory location to be
programmed (or verified). (Note: P3.5 does not have the strong pullup that is on for 2 oscillator
periods.)
Port 3 also serves the special function as listed below:
3 I ECI (P3.6): External PCA clock input.
1 I RxD/T0 (P3.4): Serial port receiver data input.
Timer 0 external clock input.
4 I INT1: External interrupt 1.
2 I TxD/T1 (P3.5): Serial port transmitter data.
Timer 1 external clock input.
RST
5 I Reset: A high on this pin for two machine cycles while the oscillator is running resets the device. After
the device is reset, a 10-bit serial sequence, sent LSB first, applied to RESET, places the device in the
programming state allowing programming address, data and VPP to be applied for programming or
verification purposes. The RESET serial sequence must be synchronized with the X1 input. (Note: The
83/87C754 does not have an internal reset resistor.)
X1 7 I Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. X1
also serves as the clock to strobe in a serial bit stream into RESET to place the device in the
programming state.
X2
AVCC 1
AVSS 1
ZIN
6 O Crystal 2: Output from the inverting oscillator amplifier.
14 I Analog supply voltage and reference input.
13 I Analog supply and reference ground.
9 I ZIN: Input to analog multiplexer.
YIN 10 I YIN: Input to analog multiplexer.
XIN 11 I XIN: Input to analog multiplexer.
XYZRAMP
12 O XYZRAMP: Provides a low impedance pulldown to VSS under S/W control.
DECOUPLE 15 O Decouple: Output from regulated supply for connection of decoupling capacitors.
VREG
16 O VREG: Provides regulated analog supply output.
XYDACBIAS
17
O XYDACBIAS: Provides source voltage for bias of external circuitry.
Input which specifies verify mode (output enable) or the program mode.
/PGM = 1 output enabled (verify mode).
/PGM = 0 program mode.
XYSOURCE
18
O XYSOURCE: Provides source voltage from regulated analog supply.
ZDAC
19 O ZDAC: Switchable outp from the internal DAC.
ASEL (P0.0) – Input which indicates which bits of the EPROM address are applied to port 3.
ASEL = 0 low address byte available on port 3.
ASEL = 1 high address byte available on port 3 (only the three least significant bits are used).
XYDAC
20 O XYDAC: Non-switchable output from the internal DAC.
NOTE:
1. AVSS (reference ground) must be connected to 0V (ground). AVCC (reference input) cannot differ from VCC by more than ±0.2V, and must be
in the range 4.5V to 5.5V.
1998 Apr 23
4

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87C754 전자부품, 판매, 대치품
Philips Semiconductors
80C51 8-bit microcontroller family
4K/256 OTP/ROM, DAC, comparator, UART, reference
Preliminary specification
83C754/87C754
DIFFERENCES BETWEEN THE 8XC754 AND THE
80C51
Program Memory
On the 8XC754, program memory is 4096 bytes long and is not
externally expandable, so the 80C51 instructions MOVX, LJMP, and
LCALL are not implemented. If these instructions are executed, the
appropriate number of instruction cycles will take place along with
external fetches; however, no operation will take place. The LJMP
may not respond to all program address bits. The only fixed
locations in program memory are the addresses at which execution
is taken up in response to reset and interrupts, which are as follows:
Program Memory
Event
Address
Reset
000
External INT0
003
Timer 0
00B
External INT1
013
PCA
01B
SIO/TF1
023
Memory Organization
The 8XC754 manipulates operands in three memory address
spaces. The first is the program memory space which contains
program instructions as well as constants such as look-up tables.
The program memory space contains 4k bytes in the 8XC754.
The second memory space is the data memory array which has a
logical address space of 256 bytes.
The third memory space is the special function register array having
a 128-byte address space (80H to FFH). Only selected locations in
this memory space are used (see Table 2). Note that the
architecture of these memory spaces (internal program memory,
internal data memory, and special function registers) is identical to
the 80C51, and the 8XC754 varies only in the amount of memory
physically implemented.
The 8XC754 does not directly address any external data or program
memory spaces. For this reason, the MOVX instructions in the
80C51 instruction set are not implemented in the 83C754, nor are
the alternate I/O pin functions RD and WR.
I/O Ports
The I/O pins provided by the 8XC754 consist of port 1 and port 3.
Port 1
Port 1 is a 3-bit bidirectional I/O port and includes alternate functions
on some pins of this port. P1.1 is provided with internal pullups while
the remaining pins (P1.0 and P1.2) are an open drain output
structure. The alternate functions for port 1 are:
INT0 – External interrupt 0.
PCAOUT – PCA clock output
VPP – External programming voltage.
Port 3
Port 3 is an 8-bit bidirectional I/O port structure. P3.5 is open drain.
The alternate functions for port 3 are:
RxD – Serial port receiver data input.
T1 – Timer 1 external clock input.
INT1 – External interrupt 1.
TxD – Serial port transmitter data.
T0 – Timer 0 external clock input.
ECI – PCA external clock input.
Analog Section
The analog section of the 8XC754, shown in Figure 3, consists of
four major elements: a bandgap referenced voltage regulator, an
8-bit DAC, an input multiplexer and comparator, and a low
impedance pulldown device.
The bandgap voltage regulator uses the AVCC pin as its supply and
produces a regulated output on the VREG pin. The bandgap
reference is enabled/disabled by AC0. The regulator also supplies
the analog supply voltage for the DAC. The regulator may be
switched on/off by means of the AC1 bit in the analog control
register (ACON0). The regulator output may also be supplied to the
XYDACBIAS and XYSOURCE pins by means of bits AC3 and AC4,
respectively. The DECOUPLE pin is provided for decoupling the
regulator output.
The DAC is an 8-bit device and its output appears on the XYDAC
pin. In addition, the DAC output may also be routed to the ZDAC pin
by means of bit AC6 in the ACON0 register. The DAC output is not
buffered, so external load impedances should be taken into
consideration when using either of these outputs.
A 3-input multiplexer is provided, whose output is connected to the
positive reference of a comparator. The multiplexer output is
controlled by bits MUX2:0 of ACON1. A bandgap reference supplies
the negative reference of the comparator. The output of the
comparator may be used the trigger the capture input of PCA
module.
A low impedance pulldown is supplied at the XYZRAMP pin and is
controlled by bit AC5 of ACON0.
Interrupt Subsystem—Fixed Priority
The interrupt structure is a seven-source, two-level interrupt system.
Simultaneous interrupt conditions are resolved by a single-level,
fixed priority as follows:
Highest priority:
Lowest priority:
Pin INT0
Timer flag 0
Pin INT1
PCA
Serial I/O – TF1
The vector addresses are as follows:
Source
INT0
TF0
INT1
PCA
SIO/TF1
Vector Address
0003H
000BH
0013H
001BH
0023H
Interrupt Enable Register
MSB
LSB
EA –
ES/T1
EC
EX1 ET0 EX0
Position
IE.7
IE.6
IE.5
IE.4
IE.3
IE.2
IE.1
IE.0
Symbol
EA
ES/T1
EC
EX1
ET0
EX0
Function
Global interrupt disable when EA = 0
Serial port/Timer Flag 1
PCA interrupt
External interrupt 1
Timer 0 overflow
External interrupt 0
1998 Apr 23
7

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