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8XC196KB16 데이터시트 PDF




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8XC196KB16 데이터시트, 핀배열, 회로
8XC196KB 8XC196KB16
COMMERCIAL EXPRESS CHMOS MICROCONTROLLER
Y 8 Kbytes of On-Chip ROM OTP
Available
Y 232 Byte Register File
Y Register-to-Register Architecture
Y 28 Interrupt Sources 16 Vectors
Y 1 75 ms 16 x 16 Multiply (16 MHz)
Y 3 0 ms 32 16 Divide (16 MHz)
Y Powerdown and Idle Modes
Y Five 8-Bit I O Ports
Y 16-Bit Watchdog Timer
Y 12 MHz and 16 MHz Available
Y Dedicated 15-Bit Baud Rate Generator
Y Dynamically Configurable 8-Bit or
16-Bit Buswidth
Y Full Duplex Serial Port
Y High Speed I O Subsystem
Y 16-Bit Timer
Y 16-Bit Up Down Counter with Capture
Y Pulse-Width-Modulated Output
Y Four 16-Bit Software Timers
Y 10-Bit A D Converter with Sample Hold
Y HOLD HLDA Bus Protocol
Y Extended Temperature Available
The 8XC196KB is a 16-bit microcontroller available in three different memory varieties ROMless (80C196KB)
8K ROM (83C196KB) and 8K OTP (One Time Programmable 87C196KB) The 8XC196KB is a high perform-
ance member of the MCS 96 microcontroller family The 8XC196KB has the same peripheral set as the
8096BH and has a true superset of the 8096BH instructions Intel’s CHMOS process provides a high perform-
ance processor along with low power consumption To further reduce power requirements the processor can
be placed into Idle or Powerdown Mode
Bit byte word and some 32-bit operations are available on the 80C196KB With a 16 MHz oscillator a 16-bit
addition takes 0 50 ms and the instruction times average 0 37 ms to 1 1 ms in typical applications
Four high-speed capture inputs are provided to record times when events occur Six high-speed outputs are
available for pulse or waveform generation The high-speed output can also generate four software timers or
start an A D conversion Events can be based on the timer or up down counter Also provided on-chip are an
A D converter serial port watchdog timer and a pulse-width-modulated output signal
The 8XC196KB has a maximum guaranteed frequency of 12 MHz The 8XC196KB16 has a maximum guaran-
teed frequency of 16 MHz All references to the 80C196KB also refer to the 80C196KB16 83C196KB Rxxx
87C196KB and 87C196KB16 unless otherwise noted The ROM device does not have a speed indicator at the
end of the device name Instead it has a ROM code number
With the commercial (standard) temperature option operational characteristics are guaranteed over the tem-
perature range of 0 C to a70 C With the extended temperature range option operational characteristics are
guaranteed over the temperature range of b40 C to a85 C
Package Designators N e 68-pin PLCC S e 80-pin QFP (commercial only) Prefix Designators T e Extend-
ed Temperature
Other brands and names are the property of their respective owners
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT INTEL CORPORATION 1995
July 1994
Order Number 270909-006




8XC196KB16 pdf, 반도체, 판매, 대치품
8XC196KB 8XC196KB16
270909 – 3
Figure 3 68-Pin Package (PLCC Top View)
NOTE
The above pin out diagram applies to the OTP (87C196KB) device The OTP device uses all of the programming pins shown
above The ROM (83C196KB) device only uses programming pins AINC PALE PMODE n and PROG The ROMless
(80C196KB) doesn’t use any of the programming pins
4

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8XC196KB16 전자부품, 판매, 대치품
8XC196KB 8XC196KB16
PIN DESCRIPTIONS (Continued)
Symbol
Name and Function
Port 0
8-bit high impedance input-only port Three pins can be used as digital inputs and or as
analog inputs to the on-chip A D converter
Port 1
8-bit quasi-bidirectional I O port These pins are shared with HOLD HLDA and BREQ
Port 2
8-bit multi-functional port All of its pins are shared with other functions in the 87C196KB
Pins P2 6 and P2 7 are quasi-bidirectional
Ports 3 and 4 8-bit bidirectional I O ports with open drain outputs These pins are shared with the
multiplexed address data bus which has strong internal pullups
HOLD
Bus Hold input requesting control of the bus Enabled by setting WSR 7
HLDA
Bus Hold acknowledge output indicating release of the bus Enabled by setting WSR 7
BREQ
Bus Request output activated when the bus controller has a pending external memory
cycle Enabled by setting WSR 7
TxD The TxD pin is used for serial port transmission in Modes 1 2 and 3 In Mode 0 the pin is
used as the serial clock output
RxD Serial Port Receive pin used for serial port reception In Mode 0 the pin functions as input or
output data
EXTINT
A rising edge on the EXTINT pin will generate an external interrupt
T2CLK
The T2CLK pin is the Timer2 clock input or the serial port baud rate generator input
T2RST
A rising edge on the T2RST pin will reset Timer2
PWM
The pulse width modulator output
T2UP-DN
The T2UPDN pin controls the direction of Timer2 as an up or down counter
T2CAPTURE A rising edge on P2 7 will capture the value of Timer2 in the T2CAPTURE register
PMODE
Programming Mode Select Determines the EPROM programming algorithm that is
performed PMODE is sampled after a chip reset and should be static while the part is
operating
SID Slave ID Number Used to assign each slave a pin of Port 3 or 4 to use for passing
programming verification acknowledgement
PALE
Programming ALE Input Accepted by the 87C196KB when it is in Slave Programming
Mode Used to indicate that Ports 3 and 4 contain a command address
PROG
Programming Falling edge indicates valid data on PBUS and the beginning of
programming Rising edge indicates end of programming
PACT
Programming Active Used in the Auto Programming Mode to indicate when programming
activity is complete
PVAL
Program Valid This signal indicates the success or failure of programming in the Auto
Programming Mode A zero indicates successful programming
PVER
Program Verification Used in Slave Programming and Auto CLB Programming Modes
Signal is low after rising edge of PROG if the programming was not successful
AINC
Auto Increment Active low signal indicates that the auto increment mode is enabled Auto
Increment will allow reading or writing of sequential EPROM locations without address
transactions across the PBUS for each read or write
Ports 3
and 4
(Programming
Mode)
Address Command Data Bus Used to pass commands addresses and data to and from
slave mode 87C196KBs Used by chips in Auto Programming Mode to pass command
addresses and data to slaves Also used in the Auto Programming Mode as a regular
system bus to access external memory Should have pullups to VCC when used in slave
programming mode
7

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