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PDF 8XC196NT Data sheet ( Hoja de datos )
| Número de pieza | 8XC196NT | |
| Descripción | CHMOS MICROCONTROLLER WITH 1 MBYTE LINEAR ADDRESS SPACE | |
| Fabricantes | Intel Corporation | |
| Logotipo |  |
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8XC196NT
CHMOS MICROCONTROLLER WITH
1 MBYTE LINEAR ADDRESS SPACE
Y 20 MHz Operation
Y High Performance CHMOS 16-Bit CPU
Y Up to 32 Kbytes of On-Chip OTPROM
Y Up to 1 Kbyte of On-Chip Register RAM
Y Up to 512 Bytes of Internal RAM
Y Register-Register Architecture
Y 4 Channel 10-Bit A D with Sample Hold
Y 37 Prioritized Interrupt Sources
Y Up to Seven 8-Bit (56) I O Ports
Y Full Duplex Serial I O Port
Y Dedicated Baud Rate Generator
Y Interprocessor Communication Slave
Port
Y Selectable Bus Timing Modes for
Flexible External Memory Interfacing
Y Oscillator Fail Detection Circuitry
Y High Speed Peripheral Transaction
Server (PTS)
Y Two Dedicated 16-Bit High-Speed
Compare Registers
Y 10 High Speed Capture Compare (EPA)
Y Full Duplex Synchronous Serial I O
Port (SSIO)
Y Two Flexible 16-Bit Timer Counters
Y Quadrature Counting Inputs
Y Flexible 8- 16-Bit External Bus
(Programmable)
Y Programmable Bus (HOLD HLDA)
Y 1 4 ms 16 x 16 Multiply
Y 2 4 ms 32 16 Divide
Y 68-Pin Package
Device
Pins Package
OTPROM
Reg
RAM
Code
RAM
Address
Space
IO
EPA
AD
8XC196NT 68P PLCC
X e 7 OTPROM Device
X e 0 ROMLESS
32K
1K 512 1 Mbyte 56 10
4
The 8XC196NT 16-bit microcontroller is a high performance member of the MCS 96 microcontroller family
The 8XC196NT is an enhanced 8XC196KR device with 1 Mbyte of linear address space 1000 bytes of
register RAM 512 bytes of internal RAM 20 MHz operation and an optional 32 Kbytes of OTPROM Intel’s
CHMOS III-E process provides a high performance processor along with low power consumption
Ten high-speed capture compare modules are provided As capture modules event times with 200 ns resolu-
tion can be recorded and generate interrupts As compare modules events such as toggling of a port pin
starting an A D conversion pulse width modulation and software timers can be generated Events can be
based on the timer or up down counter
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT INTEL CORPORATION 1995
September 1994
Order Number 272267-004
1 page  
8XC196NT
PIN DESCRIPTIONS
Symbol
Name and Function
VCC
VSS VSS1 VSS1
Main supply voltage (a5V)
Digital circuit ground (0V) There are multiple VSS pins all of which MUST be
connected
VREF
Reference for the A D converter (a5V) VREF is also the supply voltage to the
analog portion of the A D converter and the logic used to read Port 0 Must be
connected for A D and Port 0 to function
VPP Programming voltage for the OTPROM parts It should be a12 5V for programming
It is also the timing pin for the return from powerdown circuit Connect to VCC if
powerdown not being used
ANGND
XTAL1
Reference ground for the A D converter Must be held at nominally the same
potential as VSS
Input of the oscillator inverter and the internal clock generator
XTAL2
Output of the oscillator inverter
P2 7 CLKOUT
Output of the internal clock generator The frequency is the oscillator frequency
It has a 50% duty cycle Also LSIO pin
RESET
Reset input to and open-drain output from the chip RESET has an internal pullup
P5 7 BUSWIDTH
Input for bus width selection If CCR bit 1 is a one and CCR1 bit 2 is a one this pin
dyamically controls the Buswidth of the bus cycle in progress If BUSWIDTH is low
an 8-bit cycle occurs if BUSWIDTH is high a 16-bit cycle occurs If CCR bit 1 is ‘‘0’’
and CCR1 bit 2 is ‘‘1’’ all bus cycles are 8-bit if CCR bit 1 is ‘‘1’’ and CCR1 bit 2 is
‘‘0’’ all bus cycles are 16-bit CCR bit 1 e ‘‘0’’ and CCR1 bit 2 e ‘‘0’’ is illegal Also
an LSIO pin when not used as BUSWIDTH
NMI A positive transition causes a non maskable interrupt vector through memory
location 203EH
P5 1 INST SLPCS
Output high during an external memory read indicates the read is an instruction
fetch INST is valid throughout the bus cycle INST is active only during external
memory fetches during internal OTPROM fetches INST is held low Also LSIO when
not INST SLPCS is the Slave Port Chip Select
EA Input for memory select (External Access) EA equal to a high causes memory
accesses to locations 0FF2000H through 0FF9FFFH to be directed to on-chip
OTPROM EA equal to a low causes accesses to these locations to be directed to
off-chip memory EA e a12 5V causes execution to begin in the Programming
Mode EA is latched at reset
HOLD
Bus Hold Input requesting control of the bus
HLDA
Bus Hold acknowledge output indicating release of the bus
BREQ
Bus Request output activated when the bus controller has a pending external
memory cycle
P5 0 ALE ADV
SLPADDR
SLPALE
Address Latch Enable or Address Valid output as selected by CCR Both pin
options provide a latch to demultiplex the address from the address data bus When
the pin is ADV it goes inactive (high) at the end of the bus cycle ADV can be used
as a chip select for external memory ALE ADV is active only during external
memory accesses Also LSIO when not used as ALE SLPADDR is the Slave Port
Address Control Input and SLPALE is the Slave Port Address Latch Enable Input
P5 3 RD SLPRD
Read signal output to external memory RD is active only during external memory
reads or LSIO when not used as RD SLPRD is the Slave Port Read Control Input
5
5 Page 
8XC196NT
BUS MODE 0 and 3 AC CHARACTERISTICS (Over Specified Operating Conditions)
Test Conditions Capacitance Load on All Pins e 100 pF Rise and Fall Times e 10 ns
The 8XC196NT will meet these specifications
Symbol
FXTAL
TOSC
TXHCH
TOFD
TCLCL
TCHCL
TCLLH
TLLCH
TLHLH
TLHLL
TAVLL
TLLAX
TLLRL
TRLCL
TRLRH
TRHLH
TRLAZ
TLLWL
TCLWL
TQVWH
TCHWH
TWLWH
TWHQX
TWHLH
TWHBX
TWHAX
TRHBX
TRHAX
Parameter
Frequency on XTAL1
XTAL1 Period (1 FXTAL)
XTAL1 High to CLKOUT High or Low
Clock Failure to Reset Pulled Low(6)
CLKOUT Period
CLKOUT High Period
CLKOUT Low to ALE ADV High
ALE ADV Low to CLKOUT High
ALE ADV Cycle Time
ALE ADV High Time
Address Valid to ALE Low
Address Hold After ALE ADV Low
ALE ADV Low to RD Low
RD Low to CLKOUT Low
RD Low Period
RD High to ALE ADV High
RD Low to Address Float
ALE ADV Low to WR Low
CLKOUT Low to WR Low
Data Valid before WR High
CLKOUT High to WR High
WR Low Period
Data Hold after WR High
WR High to ALE ADV High
BHE INST Hold after WR High
AD8–15 Hold after WR High
BHE INST Hold after RD High
AD8–15 Hold after RD High
Min Max
4 0 20
50 250
a20
110
4 40
2 TOSC
TOSC b 10
TOSC a 30
b10
a15
b25
a15
4 TOSC
TOSC b 10
TOSC a 10
TOSC b 15
TOSC b 40
TOSC b 40
b5 a35
TOSC b 5
TOSC
TOSC a 25
a5
TOSC b 10
b10
a25
TOSC b 23
b10
a15
TOSC b 30
TOSC b 35
TOSC b 10
TOSC b 10
TOSC b 30
TOSC b 10
TOSC b 30
TOSC a 15
Units
MHz(1)
ns
ns
ms
ns
ns
ns
ns
ns(5)
ns
ns
ns
ns
ns
ns(5)
ns(3)
ns
ns
ns
ns
ns
ns(5)
ns
ns(3)
ns
ns(4)
ns
ns(4)
NOTES
1 Testing performed at 8 0 MHz however the device is static by design and will typically operate below 1 Hz
2 Typical specifications not guaranteed
3 Assuming back-to-back bus cycles
4 8-bit bus only
5 If wait states are used add 2 TOSC c n where n e number of wait states If mode 0 (1 automatic wait state added)
operation is selected add 2 TOSC to specification
6 TOFD is the time for the oscillator fail detect circuit (OFD) to react to a clock failure The OFD circuitry is enabled by
programming the UPROM location 0778H with the value 0004H NT NQ customer QROM codes need to equate location
2016H to the value 0CDEH if the oscillator fail detect (OFD) function is desired Intel manufacturing uses location 2016H
as a flag to determine whether or not to program the Clock Detect Enable (CDE) bit Programming the CDE bit
enables oscillator fail detection
11
11 Page | ||
| Páginas | Total 31 Páginas | |
| PDF Descargar | [ Datasheet 8XC196NT.PDF ] | |
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