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PDF SRM20V100 Data sheet ( Hoja de datos )
| Número de pieza | SRM20V100 | |
| Descripción | 1M-Bit Static RAM | |
| Fabricantes | Epson Company | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de SRM20V100 (archivo pdf) en la parte inferior de esta página. Total 8 Páginas | ||
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PF805-04
SRM20SVRM12000V1L0L0LMLMXX77
1M-Bit Static RAM
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q Low Supply Voltage
q Wide Temperature Range
q Low Supply Current
s DESCRIPTION
q Access Time 70ns (2.7V)
q 131,072 Words×8-Bit Asynchronous
The SRM20V100LLMX7 is an 131,072 words×8-bit asynchronous, static, random access memory on a monolithic
CMOS chip. Its very low standby power requirement makes it ideal for applications requiring non-volatile storage
with back-up batteries. And —25 to 85°C operating temperature range makes it ideal for portable equipment.
The asynchronous and static nature of the memory requires no external clock or refreshing circuit. Both the
input and output ports are TTL compatible and 3-state output allows easy expansion of memory capacity.
s FEATURES
q Wide temperature range ..... –25 to 85°C
q Fast Access time ................. SRM20V100LLMX7 70ns (Max.)
q Low supply current .............. standby: 0.6µA (Typ.): LL Version
0.3µA (Typ.): SL Version
operation: 8mA/1MHz (Typ.)
q Completely static ................. No clock required
q Supply voltage..................... 2.7V to 3.6V
q TTL compatible inputs and outputs
q 3-state output with wired-OR capability
q Non-volatile storage with back-up batteries
s PIN CONFIGURATION
(SOP6)
N.C. 1
A16 2
A14 3
A12 4
A7 5
A6 6
A5 7
A4 8
A3 9
A2 10
A1 11
A0 12
I/01 13
I/02 14
I/03 15
VSS 16
32 VDD
31 A15
30 CS2
29 WE
28 A13
27 A8
26 A9
25 A11
24 OE
23 A10
22 CS1
21 I/08
20 I/07
19 I/06
18 I/05
17 I/04
q Package ...... SRM20V100LLMX7 SOP6-32pin (plastic)
SRM20V100LLTX7 TSOP ( I )-32pin (plastic)
(TSOP/Slim-TSOP)
SRM20V100LLRX7
SRM20V100LLKX7
SRM20V100LLYX7
s BLOCK DIAGRAM
TSOP ( I )-32pin-R1 (plastic)
Slim-TSOP ( I )-32pin (plastic)
Slim-TSOP ( I )-32pin-R1 (plastic)
A11
A9
A8
A13
WE
CS2
A15
VDD
N.C.
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SRM20V100LLTX/KX
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A0
A1
A2
A3
A4
10
1024
Memory Cell Array
A5 1024×128×8
A6
A7
A8
A9
A10
A11 128×8
A12
A13 7 128 Column Gate
A14
A15
A16
(TSOP-R1/Slim-TSOP-R1)
A4
A5
A6
A7
A12
A14
A16
N.C.
VDD
A15
CS2
WE
A13
A8
A9
A11
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
SRM20V100LLRX/YX
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
OE
A10
CS1
I/08
I/07
I/06
I/05
I/04
VSS
I/03
I/02
I/01
A0
A1
A2
A3
A3
A2
A1
A0
I/01
I/02
I/03
VSS
I/04
I/05
I/06
I/07
I/08
CS1
A10
OE
CS1 8 ¡PIN DESCRIPTION
CS2
A0 to A16 Address Input
WE Write Enable
OE OE Output Enable
I/O Buffer
CS1, CS2 Chip Select
WE I/O1 to I/O8 Data I/O
VDD Power Supply (2.7V to 3.6V)
I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8
VSS
N. C.
Power Supply (0V)
No connection
1
1 page  
SRM20V100LLMX7
s FUNCTIONS
q Truth Table
CS1
H
X
L
L
L
X : "H" or "L"
CS2
X
L
H
H
H
OE
WE
DATA I/O
Mode
IDD
XX
XX
Hi-Z
Hi-Z
Unselected
Unselected
IDDS, IDDS1
IDDS, IDDS1
X
L
Input data
Write
IDDO
L
H
Output data
Read
IDDO
HH
Hi-Z Output disable
IDDO
q Reading data
Data is able to be read when the address is set while holding CS1 = "L", CS2 = "H", OE = "L" and WE = "H".
Since DATA I/O terminals are in high impedance state when OE = "H", the data bus line can be used for any
other objective, then access time apparently is able to be cut down.
q Writing data
There are the following four ways of writing data into the memory.
(1) Hold CS2 = "H", WE = "L", set addresses and give "L" pulse to CS1.
(2) Hold CS1 = "L", WE = "L" ,set addresses and give "H"pulse to CS2.
(3) Hold CS1 = "L", CS2 = "H", set addresses and give "L" pulse to WE.
(4) After setting addresses, give "L" pulse to CS1, WE and give "H" pulse to CS2.
Anyway, data on the Data I/O terminals are latched up into the SRM20V100LLMX7 at the end of the period that
CS1, WE are "L" level, and CS2 is "H" level. As Data I/O terminals are in high impedance state when any of
CS1, OE = "H", or CS2 = "L", the contention on the data bus can be avoided.
q Standby mode
When CS1 is "H" or CS2 is "L" level, the SRM20V100LLMX7 is in the standby mode which has retaining data
operation. In this case Data I/O terminals are Hi-Z, and all inputs of addresses, WE and data can be any "H" or
"L". When CS1 and CS2 level are in the range over VDD-0.2V, CS2 level is in the range under 0.2V, in the
SRM20V100LLMX7 there is almost no current flow except through the high resistance parts of the memory.
5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet SRM20V100.PDF ] | |
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