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93C06 데이터시트 PDF




Microchip Technology에서 제조한 전자 부품 93C06은 전자 산업 및 응용 분야에서
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부품번호 93C06 기능
기능 256 Bit/1K 5.0V CMOS Serial EEPROM
제조업체 Microchip Technology
로고 Microchip Technology 로고


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93C06 데이터시트, 핀배열, 회로
93C06/46
256 Bit/1K 5.0V CMOS Serial EEPROM
FEATURES
• Low power CMOS technology
• 16 bit memory organization
- 6 x 16 bit organization (93C06)
- 64 x 16 bit organization (93C46)
• Single 5 volt only operation
• Self-timed ERASE and WRITE cycles
• Automatic ERASE before WRITE
• Power on/off data protection circuitry
• 1,000,000 ERASE/WRITE cycles guaranteed
• Data Retention > 200 years
• 8-pin DIP or SOIC package
• Available for extended temperature ranges:
- Commercial: 0˚C to +70˚C
- Industrial: -40˚C to +85˚C
- Automotive: -40˚C to +125˚C
• 2 ms program cycle time
DESCRIPTION
The Microchip Technology Inc. 93C06/46 family of
Serial Electrically Erasable PROMs are configured in a
x16 organization. Advanced CMOS technology makes
these devices ideal for low-power non-volatile memory
applications. The 93C06/46 is available in the standard
8-pin DIP and surface mount SOIC packages. The
93C46X comes as SOIC only.
These devices offer fast (1 ms) byte write and extended
(-40˚C to +125˚C) temperature operation. It is recom-
mended that all other applications use Microchip’s
93LC46.
PACKAGE TYPE
DIP
CS 1
8 VCC
CLK 2 93C06 7 NC
93C46
DI 3
6 NC
DO 4
5 VSS
SOIC
CS
CLK
DI
DO
18
27
93C06
3 93C46 6
45
VCC
NC
NC
VSS
NC
VCC
CS
CLK
18
27
93C46X
36
45
NC
VSS
DO
DI
BLOCK DIAGRAM
VCC
VSS
MEMORY
ARRAY
ADDRESS
DECODER
DATA REGISTER
DI
MODE
DECODE
CS LOGIC
CLOCK
CLK
GENERATOR
OUTPUT
BUFFER
DO
© 1995 Microchip Technology Inc.
DS11179C-page 1




93C06 pdf, 반도체, 판매, 대치품
93C06/46
The status signal is not available on DO, if CS is held
LOW or HIGH during the entire WRITE or ERASE
cycle. In all other cases DO is in the HIGH-Z mode. If
status is checked after the WRITE/ERASE cycle, a
pull-up resistor on DO is required to read the READY
signal.
DI and DO can be connected together to perform a 3-
wire interface (CS, CLK, DI/DO).
Care must be taken with the leading dummy zero which
is outputted after a READ command has been
detected. Also, the controlling device must not drive
the DI/DO bus during Erase and Write cycles if the
READY/BUSY status information is outputted by the
93C06/46.
INSTRUCTION SET - 93C06
Instruction Start BIT
Opcode
OP1 OP2
READ
WRITE
ERASE
EWEN
EWDS
ERAL
WRAL
1 10
1 01
1 11
1 00
1 00
1 00
1 00
INSTRUCTION SET - 93C46
Instruction
READ
WRITE
ERASE
EWEN
EWDS
ERAL
WRAL
Start BIT
1
1
1
1
1
1
1
Opcode
OP1 OP2
10
01
11
00
00
00
00
Address
0 0 A3 A2 A1 A0
0 0 A3 A2 A1 A0
0 0 A3 A2 A1 A0
11 X X X X
00 X X X X
10 X X X X
01 X X X X
Address
A5 A4 A3 A2 A1 A0
A5 A4 A3 A2 A1 A0
A5 A4 A3 A2 A1 A0
11XXXX
00XXXX
10XXXX
01XXXX
Number of
Data In
D15 - D0
D15 - D0
Number of
Data In
D15 - D0
D15 - D0
Data Out
D15 - D0
(RDY/BSY)
(RDY/BSY)
High-Z
High-Z
(RDY/BSY)
(RDY/BSY)
Data Out
D15 - D0
(RDY/BSY)
(RDY/BSY)
High-Z
High-Z
(RDY/BSY)
(RDY/BSY)
Req. CLK
Cycles
25
25
9
9
9
9
25
Req. CLK
Cycles
25
25
9
9
9
9
25
3.0 FUNCTIONAL DESCRIPTION
3.1 START Condition
The START bit is detected by the device if CS and DI
are both HIGH with respect to the positive edge of CLK
for the first time.
Before a START condition is detected, CS, CLK, and DI
may change in any combination (except to that of a
START condition), without resulting in any device oper-
ation (READ, WRITE, ERASE, EWEN, EWDS, ERAL,
and WRAL). As soon as CS is HIGH, the device is no
longer in the standby mode.
An instruction following a START condition will only be
executed if the required amount of opcode, address
and data bits for any particular instruction is clocked in.
After execution of an instruction (i.e., clock in or out of
the last required address or data bit) CLK and DI
become don't care bits until a new start condition is
detected.
3.2 DI/DO
It is possible to connect the Data In and Data Out pins
together. However, with this configuration it is possible
for a “bus conflict” to occur during the “dummy zero”
that precedes the READ operation, if A0 is a logic HIGH
level. Under such a condition the voltage level seen at
Data Out is undefined and will depend upon the relative
impedances of Data Out and the signal source driving
A0. The higher the current sourcing capability of A0,
the higher the voltage at the Data Out pin.
3.3 Data Protection
During power-up, all modes of operation are inhibited
until VCC has reached 2.8V. During power-down, the
source data protection circuitry acts to inhibit all modes
when VCC has fallen below 2.8V.
The EWEN and EWDS commands give additional pro-
tection against accidentally programming during nor-
mal operation.
After power-up, the device is automatically in the
EWDS mode. Therefore, an EWEN instruction must be
performed before any ERASE or WRITE instruction
can be executed. After programming is completed, the
EWDS instruction offers added protection against unin-
tended data changes.
DS11179C-page 4
© 1995 Microchip Technology Inc.

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93C06 전자부품, 판매, 대치품
93C06/46
3.8 ERASE All (ERAL)
The entire chip will be erased to logical "1s" if this
instruction is received by the device and it is in the
EWEN mode. The ERAL cycle is completely self-timed
and commences after the last dummy address bit has
been clocked in.
ERAL takes 15 ms maximum.
FIGURE 3-5: ERASE ALL
CLK
TCSL
TCSL
CS
SB OP1 OP2
DI
STATUS
CHECK
10
0
10X
XX X
T DDZ
TSV
DO
HIGH - Z
BSY RDY
T WC
NEW INSTRUCTION
OR STANDBY (CS = 0)
3.9 WRITE All (WRAL)
The entire chip will be written with the data specified in
that command. The WRAL cycle is completely self-
timed and commences after the rising edge of the CLK
for the last data bit (DO). WRAL takes 15 ms maxi-
mum.
Note:
The WRAL does not include an automatic
ERASE cycle for the chip. Therefore, the
WRAL instruction must be preceded by an
ERAL instruction and the chip must be in
the EWEN status in both cases.
The WRAL instruction is used for testing and/or device
initialization.
FIGURE 3-6: WRITE ALL
CLK
CS
SB OP1 OP2
D15
DI
1 0 0 0 1 X XX X
DO HIGH - Z
TCSL
TCSL
STATUS
CHECK
D0
TSV
BSY RDY
T WC
NEW INSTRUCTION
OR STANDBY (CS = 0)
© 1995 Microchip Technology Inc.
DS11179C-page 7

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