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93C56 데이터시트 PDF




ATMEL Corporation에서 제조한 전자 부품 93C56은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


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부품번호 93C56 기능
기능 3-Wire Serial EEPROMs
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93C56 데이터시트, 핀배열, 회로
Features
Low-voltage and Standard-voltage Operation
– 2.7 (VCC = 2.7V to 5.5V)
– 1.8 (VCC = 1.8V to 5.5V)
User-selectable Internal Organization
– 1K: 128 x 8 or 64 x 16
– 2K: 256 x 8 or 128 x 16
– 4K: 512 x 8 or 256 x 16
Three-wire Serial Interface
2 MHz Clock Rate (5V)
Self-timed Write Cycle (10 ms max)
High Reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
Automotive Grade, Extended Temperature and Lead-Free/Halogen-Free
Devices Available
8-lead PDIP, 8-lead JEDEC SOIC, 8-lead EIAJ SOIC, 8-lead MAP, 8-lead TSSOP,
and 8-ball dBGA2 Packages
Description
The AT93C46/56/66 provides 1024/2048/4096 bits of serial electrically erasable pro-
grammable read-only memory (EEPROM), organized as 64/128/256 words of 16 bits
each (when the ORG pin is connected to VCC), and 128/256/512 words of 8 bits each
(when the ORG pin is tied to ground). The device is optimized for use in many indus-
trial and commercial applications where low-power and low-voltage operations are
essential. The AT93C46/56/66 is available in space-saving 8-lead PDIP, 8-lead
JEDEC SOIC, 8-lead EIAJ SOIC, 8-lead MAP, 8-lead TSSOP, and 8-lead dBGA2
packages.
The AT93C46/56/66 is enabled through the Chip Select pin (CS) and accessed via a
three-wire serial interface consisting of Data Input (DI), Data Output (DO), and Shift
Clock (SK). Upon receiving a Read instruction at DI, the address is decoded and the
data is clocked out serially on the DO pin. The Write cycle is completely self-timed,
and no separate Erase cycle is required before Write. The Write cycle is only enabled
when the part is in the Erase/Write Enable state. When CS is brought high following
the initiation of a Write cycle, the DO pin outputs the Ready/Busy status of the part.
The AT93C46/56/66 is available in 2.7V to 5.5V and 1.8V to 5.5V versions.
Table 1. Pin Configurations
Pin Name
Function
CS Chip Select
SK Serial Data Clock
DI Serial Data Input
DO Serial Data Output
GND
Ground
VCC
Power Supply
ORG
Internal Organization
DC Don’t Connect
8-lead SOIC
8-lead dBGA2
CS 1
SK 2
DI 3
DO 4
8 VCC
7 DC
6 ORG
5 GND
VCC
DC
ORG
GND
8
7
6
5
1 CS
2 SK
3 D1
4 D0
8-lead PDIP
CS 1
SK 2
DI 3
DO 4
8 VCC
7 DC
6 ORG
5 GND
8-lead SOIC
Rotated (R)
(1K JEDEC Only)
DC
VCC
CS
SK
1
2
3
4
8 ORG
7 GND
6 DO
5 DI
8-lead MAP
VCC 8
DC 7
ORG 6
GND 5
1 CS
2 SK
3 DI
4 DO
8-lead TSSOP
CS 1
SK 2
DI 3
DO 4
8 VCC
7 DC
6 ORG
5 GND
Three-wire
Serial
EEPROMs
1K (128 x 8 or 64 x 16)
2K (256 x 8 or 128 x 16)
4K (512 x 8 or 256 x 16)
AT93C46
AT93C56(1)
AT93C66(2)
Note: 1. This device is not recom-
mended for new designs.
Please refer to AT93C56A.
2. This device is not recom-
mended for new designs.
Please refer to AT93C66A.
0172Z–SEEPR–9/05
1




93C56 pdf, 반도체, 판매, 대치품
Table 4. AC Characteristics
Applicable over recommended operating range from TAI = 40°C to + 85°C, VCC = As Specified,
CL = 1 TTL Gate and 100 pF (unless otherwise noted)
Symbol
Parameter
Test Condition
Min Typ
fSK
SK Clock
Frequency
4.5V VCC 5.5V
2.7V VCC 5.5V
1.8V VCC 5.5V
0
0
0
4.5V VCC 5.5V
tSKH
SK High Time
2.7V VCC 5.5V
1.8V VCC 5.5V
250
250
1000
4.5V VCC 5.5V
tSKL
SK Low Time
2.7V VCC 5.5V
1.8V VCC 5.5V
250
250
1000
tCS
Minimum CS
Low Time
4.5V VCC 5.5V
2.7V VCC 5.5V
1.8V VCC 5.5V
250
250
1000
4.5V VCC 5.5V
50
tCSS
CS Setup Time Relative to SK
2.7V VCC 5.5V
50
1.8V VCC 5.5V
200
4.5V VCC 5.5V
100
tDIS
DI Setup Time
Relative to SK
2.7V VCC 5.5V
100
1.8V VCC 5.5V
400
tCSH
CS Hold Time
Relative to SK
0
4.5V VCC 5.5V
100
tDIH
DI Hold Time
Relative to SK
2.7V VCC 5.5V
100
1.8V VCC 5.5V
400
tPD1
Output Delay to
“1”
AC Test
4.5V VCC 5.5V
2.7V VCC 5.5V
1.8V VCC 5.5V
tPD0
Output Delay to
“0”
AC Test
4.5V VCC 5.5V
2.7V VCC 5.5V
1.8V VCC 5.5V
tSV
CS to Status
Valid
AC Test
4.5V VCC 5.5V
2.7V VCC 5.5V
1.8V VCC 5.5V
tDF
CS to DO in High AC Test
Impedance
CS = VIL
4.5V VCC 5.5V
2.7V VCC 5.5V
1.8V VCC 5.5V
tWP
Endurance(1)
Write Cycle Time
5.0V, 25°C
4.5V VCC 5.5V
Note: 1. This parameter is characterized and is not 100% tested.
0.1
1M
3
Max
2
1
0.25
250
250
1000
250
250
1000
250
250
1000
100
100
400
10
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
Write Cycles
4 AT93C46/56/66
0172Z–SEEPR–9/05

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93C56 전자부품, 판매, 대치품
Timing Diagrams
Figure 2. Synchronous Data Timing
µs
AT93C46/56/66
Note: 1. This is the minimum SK period.
Table 7. Organization Key for Timing Diagrams
AT93C46 (1K)
AT93C56 (2K)(1)
Notes:
I/O x 8 x 16 x 8 x 16
AN
A6
A5
A8(3)
A7(4)
DN D7 D15 D7 D15
1. This device is not recommended for new designs. Please refer to AT93C56A.
2. This device is not recommended for new designs. Please refer to AT93C66A.
3. A8 is a don’t care value, but the extra clock is required.
4. A7 is a don’t care value, but the extra clock is required.
AT93C66 (4K)(2)
x 8 x 16
A8 A7
D7 D15
0172Z–SEEPR–9/05
7

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부품번호상세설명 및 기능제조사
93C56

3-Wire Serial EEPROMs

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93C56

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