Datasheet.kr   

93C66 데이터시트 PDF




Fairchild Semiconductor에서 제조한 전자 부품 93C66은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 93C66 자료 제공

부품번호 93C66 기능
기능 4096-Bit Serial CMOS EEPROM (MICROWIRE Synchronous Bus)
제조업체 Fairchild Semiconductor
로고 Fairchild Semiconductor 로고


93C66 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.




전체 13 페이지수

미리보기를 사용할 수 없습니다

93C66 데이터시트, 핀배열, 회로
July 2000
FM93C66
4096-Bit Serial CMOS EEPROM
(MICROWIRE™ Synchronous Bus)
General Description
FM93C66 is a 4096-bit CMOS non-volatile EEPROM organized
as 256 x 16-bit array. This device features MICROWIRE interface
which is a 4-wire serial bus with chipselect (CS), clock (SK), data
input (DI) and data output (DO) signals. This interface is compat-
ible to many of standard Microcontrollers and Microprocessors.
There are 7 instructions implemented on the FM93C66 for various
Read, Write, Erase, and Write Enable/Disable operations. This
device is fabricated using Fairchild Semiconductor floating-gate
CMOS process for high reliability, high endurance and low power
consumption.
“LZ” and “L” versions of FM93C66 offer very low standby current
making them suitable for low power applications. This device is
offered in both SO and TSSOP packages for small space consid-
erations.
Features
I Wide VCC 2.7V - 5.5V
I Typical active current of 200µA
10µA standby current typical
1µA standby current typical (L)
0.1µA standby current typical (LZ)
I No Erase instruction required before Write instruction
I Self timed write cycle
I Device status during programming cycles
I 40 year data retention
I Endurance: 1,000,000 data changes
I Packages available: 8-pin SO, 8-pin DIP, 8-pin TSSOP
Functional Diagram
CS
SK
DI
INSTRUCTION
REGISTER
ADDRESS
REGISTER
INSTRUCTION
DECODER
CONTROL LOGIC
AND CLOCK
GENERATORS
DECODER
EEPROM ARRAY
16
READ/WRITE AMPS
16
DATA IN/OUT REGISTER
16 BITS
DO DATA OUT BUFFER
VCC
HIGH VOLTAGE
GENERATOR
AND
PROGRAM
TIMER
VSS
© 2000 Fairchild Semiconductor International
FM93C66 Rev. C.1
1
www.fairchildsemi.com




93C66 pdf, 반도체, 판매, 대치품
Absolute Maximum Ratings (Note 1)
Operating Conditions
Ambient Storage Temperature
All Input or Output Voltages
with Respect to Ground
Lead Temperature
(Soldering, 10 sec.)
ESD rating
-65°C to +150°C
+6.5V to -0.3V
+300°C
2000V
Ambient Operating Temperature
FM93C66L/LZ
FM93C66LE/LZE
FM93C66LV/LZV
Power Supply (VCC)
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
2.7V to 5.5V
DC and AC Electrical Characteristics VCC = 2.7V to 4.5V unless otherwise specified. Refer to
page 3 for VCC = 4.5V to 5.5V.
Symbol
ICCA
ICCS
Parameter
Operating Current
Standby Current
L
LZ (2.7V to 4.5V)
Conditions
CS = VIH, SK=250 KHz
CS = VIL
Min Max Units
1 mA
10 µA
1 µA
IIL Input Leakage
IOL Output Leakage
VIL Input Low Voltage
VIH Input High Voltage
VOL Output Low Voltage
VOH Output High Voltage
fSK SK Clock Frequency
tSKH SK High Time
tSKL SK Low Time
tCS Minimum CS Low Time
tCSS CS Setup Time
tDH DO Hold Time
tDIS DI Setup Time
tCSH CS Hold Time
tDIH DI Hold Time
tPD Output Delay
tSV CS to Status Valid
tDF CS to DO in Hi-Z
tWP Write Cycle Time
VIN = 0V to VCC
(Note 2)
IOL = 10µA
IOH = -10µA
(Note 3)
(Note 4)
CS = VIL
-0.1
0.8VCC
0.9VCC
0
1
1
1
0.2
70
0.4
0
0.4
±1
0.15VCC
VCC +1
0.1VCC
250
2
1
0.4
15
µA
V
V
KHz
µs
µs
µs
µs
ns
µs
ns
µs
µs
µs
µs
ms
Capacitance TA = 25°C, f = 1 MHz or
250 KHz (Note 5)
Symbol
COUT
CIN
Test
Output Capacitance
Input Capacitance
Typ Max Units
5 pF
5 pF
AC Test Conditions
Note 1: Stress above those listed under Absolute Maximum Ratingsmay cause permanent damage
to the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect device reliability.
Note 2: Typical leakage values are in the 20nA range.
Note 3: The shortest allowable SK clock period = 1/fSK (as shown under the fSK parameter). Maximum
SK clock speed (minimum SK period) is determined by the interaction of several AC parameters stated
in the datasheet. Within this SK period, both tSKH and tSKL limits must be observed. Therefore, it is not
allowable to set 1/fSK = tSKHminimum + tSKLminimum for shorter SK cycle time operation.
Note 4: CS (Chip Select) must be brought low (to VIL) for an interval of tCS in order to reset all internal
device registers (device reset) prior to beginning another opcode cycle. (This is shown in the opcode
diagram on the following page.)
Note 5: This parameter is periodically sampled and not 100% tested.
VCC Range
2.7V VCC 5.5V
(Extended Voltage Levels)
4.5V VCC 5.5V
(TTL Levels)
VIL/VIH
Input Levels
0.3V/1.8V
VIL/VIH
Timing Level
1.0V
VOL/VOH
Timing Level
0.8V/1.5V
0.4V/2.4V
1.0V/2.0V
0.4V/2.4V
Output Load: 1 TTL Gate (CL = 100 pF)
IOL/IOH
±10µA
2.1mA/-0.4mA
FM93C66 Rev. C.1
4 www.fairchildsemi.com

4페이지










93C66 전자부품, 판매, 대치품
The Erase all instruction will program all locations to a logical 1
state. Input information (Start bit, Opcode and Address) for this
WDS instruction should be issued as listed under Table1. After
inputting the last bit of data (A0 bit), CS signal must be brought low
before the next rising edge of the SK clock. This falling edge of the
CS initiates the self-timed programming cycle. It takes tWP time
(Refer appropriate DC and AC Electrical Characteristics table) for
the internal programming cycle to finish. During this time, the
device remains busy and is not ready for another instruction.
Status of the internal programming can be polled as described
under WRITE instruction description. While the device is busy, it
is recommended that no new instruction be issued. Refer Erase
All cycle diagram.
Note: The Fairchild CMOS EEPROMs do not require an ERASEor ERASE ALL
instruction prior to the WRITEor WRITE ALLinstruction, respectively. The
ERASEand ERASE ALLinstructions are included to maintain compatibility with
earlier technology EEPROMs.Clearing of Ready/Busy status
When programming is in progress, the Data-Out pin will display
the programming status as either BUSY (low) or READY (high)
when CS is brought high (DO output will be tri-stated when CS is
low). To restate, during programming, the CS pin may be brought
high and low any number of times to view the programming status
without affecting the programming operation. Once programming
is completed (Output in READY state), the output is cleared
(returned to normal tri-state condition) by clocking in a Start Bit.
After the Start Bit is clocked in, the output will return to a tri-stated
condition. When clocked in, this Start Bit can be the first bit in a
command string, or CS can be brought low again to reset all
internal circuits. Refer Clearing Ready Status diagram.
Related Document
Application Note: AN758 - Using Fairchilds MICROWIREEE-
PROM.
FM93C66 Rev. C.1
7 www.fairchildsemi.com

7페이지


구       성 총 13 페이지수
다운로드[ 93C66.PDF 데이터시트 ]

당사 플랫폼은 키워드, 제품 이름 또는 부품 번호를 사용하여 검색할 수 있는

포괄적인 데이터시트를 제공합니다.


구매 문의
일반 IC 문의 : 샘플 및 소량 구매
-----------------------------------------------------------------------

IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한
광범위한 전력 반도체를 판매합니다.

전력 반도체 전문업체

상호 : 아이지 인터내셔날

사이트 방문 :     [ 홈페이지 ]     [ 블로그 1 ]     [ 블로그 2 ]



관련 데이터시트

부품번호상세설명 및 기능제조사
93C65

AK93C65

Asahi Kasei Microsystems
Asahi Kasei Microsystems
93C66

4096-Bit Serial CMOS EEPROM (MICROWIRE Synchronous Bus)

Fairchild Semiconductor
Fairchild Semiconductor

DataSheet.kr       |      2020   |     연락처      |     링크모음      |      검색     |      사이트맵