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PDF PM73488 Data sheet ( Hoja de datos )
| Número de pieza | PM73488 | |
| Descripción | 5 Gbit/s ATM Switch Fabric Element | |
| Fabricantes | PMC-Sierra | |
| Logotipo |  |
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Released
Datasheet
PMC-980616
Issue 3
PMC-Sierra, Inc.
PM73488 QSE
5 Gbit/s ATM Switch Fabric Element
PM73488
QSE
5 Gbit/s ATM Switch Fabric Element
DATASHEET
Released
Issue 3: June 1999
1 page  
Released
Datasheet
PMC-980616
PMC-Sierra, Inc.
PM73488 QSE
Issue 3
5 Gbit/s ATM Switch Fabric Element
3.9 Cell Timing/Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4 QSE Feature Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.1 Distribution Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.2 Cell Start Offset Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.2.1 Relation Between External CELL_START and Local CELL_START . . . . . . . . . . . . . . . . . . . . . . 47
4.2.2 Relation Between Local CELL_START and Data Out of the QSE . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.3 General Description of Phase Aligners . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.4 Multicast Backpressure Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.5 Multilevel Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5 Fault Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5. 1 Purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5. 2 Basic Data and BP/ACK Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5. 3 Fault Detection Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5. 4 Interface Behavior. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5. 5 IRT-to-Switch Fabric Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5. 6 QSE Interface, Receive Data Direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5. 7 QSE Interface, Transmit Data Direction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
5. 8 Switch Fabric-to-ORT Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
5. 9 Types of Failures and Their Manifestation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6.1 Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6.2 Signal Locations (Signal Name to Ball) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
6.3 Signal Locations (Ball to Signal Name) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
6.4 Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
6.4.1 Processor Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6.4.2 Multicast RAM Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6.4.3 QSE Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
6.4.4 Boundary Scan Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.4.5 Miscellaneous Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.4.6 Total Pin Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
7 Physical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
8 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
8.1 Microprocessor Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
8.2 RAM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
8.3 QSE Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
8.4 Miscellaneous Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
9 Microprocessor Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
9.1 Microprocessor Ports Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
9.2 Note on Error Detection and Reporting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
9.3 Microprocessor Ports Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
9.3.1 REVISION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
9.3.2 CHIP_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
5 Page 
Released
Datasheet
PMC-980616
PMC-Sierra, Inc.
PM73488 QSE
Issue 3
5 Gbit/s ATM Switch Fabric Element
W AC - 48 8 - B
Product Overview
DESCRIPTION
The PM73488 (QSE) is an advanced communications device that enables the implementation of high performance
switching systems. The QSE is a 32 × 32 cell based switch element, with a total sustainable bandwidth of 5 Gb/s.
(The peak, or raw, bandwidth is much more than that: about 8 Gb/s). The QSE is designed to be used with other
QSE’s as part of a larger switch fabric. Various QSE combinations allow fabrics with theoretical peak capacities
ranging from 5 Gb/s (one QSE) to 160 Gb/s. The QSE is not ATM specific; however, should the QSE be used for
switching ATM cells, the QSE cell size is large enough to allow efficient direct mapping between QSE Cells and
ATM cells.
Multistage QSE Fabrics (Delta-Reverse Delta configuration) have rich connectivity with multiple paths between each
source/destination pair. A QSE fabric performs cut-through unicast switching and uses Randomization and Evil-Twin
algorithms to fully utilize these multiple paths and avoid the build up of internal hot spots. Randomization, in combi-
nation with multiple routing paths allows graceful degradation of QSE Fabric performance if internal links fail. To
detect failed links, the QSE maintains and checks liveness patterns on input and output ports in hardware, and
automatically routes around ports if they die.
QSE data ports are 6 bits wide including a 4-bit wide 66 MHz data path, a one-bit wide start-of-cell indication, and a
one-bit wide acknowledgment signal. Each port contains "Phase Aligners" to recover the clock for that port, thus
removing the need to synchronize all data to a single global clock.
When switching unicast traffic in a multistage fabric (one to three stages), the first nibble of the cell will come out of
the last QSE stage before the last nibble of that cell enters the first stage. The cell thereby traverses the entire fabric in
one cell time. If the cell sucessfully makes it to its destination, the ("egress") device accepting the cell from the last
stage QSE has the opportunity to send a four bit "Ack Information Packet" back to source indicating what it did with
this cell; at its simplest, the egress device can send back one pattern to indicate that the cell was accepted and another
to indicate that the cell was dropped due to, say, buffer overflow.
It is also possible that the cell was dropped inside the QSE fabric due to say a collision with another cell. The QSE
classifies lost cells as due to one of three causes (collision, all possible outputs dead, or parity errors) and will
generate an "Ack Information Packet" back to the source to communicate this event. In each QSE, the 4 bit pattern in
the information packet can be independently software configured for each of the three cases. Note that since each
QSE can be separately programmed, the patterns can even be setup so that the source knows where the cell was
dropped.
The information provided by the "Ack Information Packets" can be used by the device injecting cells into the first
QSE stage to decide how to handle the cells; at its simplest, the device can resend cells that did not get through (a
more sophisticated algorithm might also take into account where the cell was lost and the behavior of the evil twin
algorithm to decide when to resend the cell; for example if the cell was dropped due to output congestion it might
make sense to back off on cells to that output).
For unicast traffic, part of switch bandwidth will be used to resend cells that did not make it through the first time
around. This implies that sustained throughput is less than peak switching capacity. The amount of bandwidth
required for resending cells and the effect of resending on latency and "Cell Delay Variation (CDV)" has been exten-
sively studied with analytical models of the fabric. These results have then been cross checked with results from
simulating software models of the fabric. This data is crucial for designing fabrics that can efficiently support
13
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet PM73488.PDF ] | |
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