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PDF PM7351 Data sheet ( Hoja de datos )
| Número de pieza | PM7351 | |
| Descripción | OCTAL SERIAL LINK MULTIPLEXER | |
| Fabricantes | PMC-Sierra | |
| Logotipo |  |
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RELEASED
DATA SHEET
PMC-1980582
ISSUE 5
PM7351 S/UNI-VORTEX
OCTAL SERIAL LINK MULTIPLEXER
PM7351
S/UNI -TM
VORTEX
S/UNI-VORTEX
OCTAL SERIAL LINK MULTIPLEXER
DATA SHEET
RELEASED
ISSUE 5: MARCH 2000
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
1 page  
RELEASED
DATA SHEET
PMC-1980582
ISSUE 5
PM7351 S/UNI-VORTEX
OCTAL SERIAL LINK MULTIPLEXER
LIST OF REGISTERS
REGISTER 0X000: MASTER RESET AND IDENTITY / LOAD PERFORMANCE
METERS ................................................................................................ 56
REGISTER 0X001: MASTER CONFIGURATION ............................................ 57
REGISTER 0X002: RECEIVE SERIAL INTERRUPT STATUS......................... 59
REGISTER 0X003: TRANSMIT SERIAL INTERRUPT STATUS ...................... 60
REGISTER 0X004: MISCELLANEOUS INTERRUPT STATUSES................... 61
REGISTER 0X005: CONTROL CHANNEL BASE ADDRESS .......................... 63
REGISTER 0X006: CONTROL CHANNEL BASE ADDRESS MSB ................. 64
REGISTER 0X007: CLOCK MONITOR............................................................ 65
REGISTER 0X008: DOWNSTREAM CELL INTERFACE CONFIGURATION .. 67
REGISTER 0X00A: DOWNSTREAM CELL INTERFACE INTERRUPT ENABLE
............................................................................................................... 69
REGISTER 0X00B: DOWNSTREAM CELL INTERFACE INTERRUPT STATUS
............................................................................................................... 70
REGISTER 0X00C: UPSTREAM CELL INTERFACE CONFIGURATION AND
INTERRUPT STATUS............................................................................ 71
REGISTER 0X010: MICROPROCESSOR CELL BUFFER INTERRUPT
CONTROL AND STATUS....................................................................... 73
REGISTER 0X011: MICROPROCESSOR INSERT FIFO CONTROL.............. 75
REGISTER 0X012: MICROPROCESSOR EXTRACT FIFO CONTROL .......... 77
REGISTER 0X013: MICROPROCESSOR INSERT FIFO READY................... 79
REGISTER 0X014: MICROPROCESSOR EXTRACT FIFO READY ............... 80
REGISTER 0X015: INSERT CRC-32 ACCUMULATOR (LSB)......................... 81
REGISTER 0X016: INSERT CRC-32 ACCUMULATOR (2ND BYTE) .............. 81
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE iii
5 Page 
RELEASED
DATA SHEET
PMC-1980582
ISSUE 5
PM7351 S/UNI-VORTEX
OCTAL SERIAL LINK MULTIPLEXER
1 FEATURES
• Integrated analog/digital device that interfaces a high speed parallel bus to 8
bidirectional data streams, each transported over a high speed Low Voltage
Differential Signal (LVDS) serial link.
• Works with its sister device, the S/UNI-DUPLEX, to satisfy a full set of system
level requirements for backplane interconnect:
• Transports user data by providing the inter-card data-path.
• Inter-processor communication by providing an integrated inter-card
control channel.
• Exchanges flow control information (back-pressure) to prevent data
loss.
• Provides embedded command and control signals across the
backplane: system reset, error indications, protection switching
commands, etc.
• Clock/timing distribution (system clocks as well as reference clocks
such as 8 kHz timing references).
• Fault detection, redundancy, protection switching, and
inserting/removing cards while the system is running (hot swap).
• Each S/UNI-VORTEX Interfaces to 8 S/UNI-DUPLEX devices (via the LVDS
links) to create a point-to-multipoint serial backplane architecture.
• Up to 16 S/UNI-VORTEX devices (interfacing to a maximum of 128 S/UNI-
DUPLEXs) can reside on a single system bus.
• In the LVDS receive direction: accepts cell streams from the 8 LVDS links,
multiplexing them into a single cell stream which is presented to the system
bus as a single Utopia L2 compatible PHY.
• In the LVDS transmit direction: receives cell streams from the bus master,
and routes the cells to the appropriate serial link.
• Cell read/write to the 8 LVDS links is available via the microprocessor port.
Provides optional hardware assisted CRC32 calculation across cells to create
an embedded inter-processor communication channel across the LVDS links.
• Optionally routes the embedded control channels from the 8 link's to/ from the
system bus.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 1
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet PM7351.PDF ] | |
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