|
|
PDF PM7364 Data sheet ( Hoja de datos )
| Número de pieza | PM7364 | |
| Descripción | Frame Engine and Datalink Manager | |
| Fabricantes | PMC-Sierra | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de PM7364 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
RELEASED
DATA SHEET
PMC-1960758
ISSUE 6
PM7364 FREEDM-32
FRAME ENGINE AND DATA LINK MANAGER
PM7364
FREEDM™-32
FRAME ENGINE AND DATALINK
MANAGER
DATA SHEET
ISSUE 6: AUGUST 2001
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE
1 page  
RELEASED
DATA SHEET
PMC-1960758
10
11
12
13
14
15
16
17
18
19
PM7364 FREEDM-32
ISSUE 6
FRAME ENGINE AND DATA LINK MANAGER
9.11 PCI HOST INTERFACE ...............................................................73
NORMAL MODE REGISTER DESCRIPTION ........................................79
10.1 PCI HOST ACCESSIBLE REGISTERS .......................................79
PCI CONFIGURATION REGISTER DESCRIPTION ............................251
11.1 PCI CONFIGURATION REGISTERS.........................................251
TEST FEATURES DESCRIPTION .......................................................262
12.1 TEST MODE REGISTERS ........................................................262
12.2 JTAG TEST PORT .....................................................................263
12.2.1 IDENTIFICATION REGISTER .....................................264
12.2.2 BOUNDARY SCAN REGISTER ..................................264
OPERATIONS ......................................................................................278
13.1 EQUAD CONNECTIONS...........................................................278
13.2 TOCTL CONNECTIONS ............................................................278
13.3 JTAG SUPPORT........................................................................279
FUNCTIONAL TIMING .........................................................................285
14.1 RECEIVE LINK INPUT TIMING .................................................285
14.2 TRANSMIT LINK OUTPUT TIMING...........................................286
14.3 PCI INTERFACE ........................................................................288
14.4 BERT INTERFACE ....................................................................297
ABSOLUTE MAXIMUM RATINGS........................................................299
D.C. CHARACTERISTICS....................................................................300
FREEDM-32 TIMING CHARACTERISTICS .........................................302
ORDERING AND THERMAL INFORMATION ......................................308
MECHANICAL INFORMATION.............................................................309
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE iv
5 Page 
RELEASED
DATA SHEET
PMC-1960758
ISSUE 6
PM7364 FREEDM-32
FRAME ENGINE AND DATA LINK MANAGER
LIST OF FIGURES
FIGURE 1 – HDLC FRAME...............................................................................31
FIGURE 2 – CRC GENERATOR.......................................................................32
FIGURE 3 – PARTIAL PACKET BUFFER STRUCTURE ..................................36
FIGURE 4 – RECEIVE PACKET DESCRIPTOR...............................................38
FIGURE 5 – RECEIVE PACKET DESCRIPTOR TABLE...................................41
FIGURE 6 – RPDRF AND RPDRR QUEUES ...................................................43
FIGURE 7 – RPDRR QUEUE OPERATION......................................................45
FIGURE 8 – RECEIVE CHANNEL DESCRIPTOR REFERENCE TABLE.........46
FIGURE 9 – GPIC ADDRESS MAP ..................................................................53
FIGURE 10 – TRANSMIT DESCRIPTOR .........................................................55
FIGURE 11 – TRANSMIT DESCRIPTOR TABLE .............................................59
FIGURE 12 – TDRR AND TDRF QUEUES .......................................................61
FIGURE 13 – TRANSMIT CHANNEL DESCRIPTOR REFERENCE TABLE ....63
FIGURE 14 – TD LINKING................................................................................66
FIGURE 15 – PARTIAL PACKET BUFFER STRUCTURE ................................70
FIGURE 16 – INPUT OBSERVATION CELL (IN_CELL) .................................275
FIGURE 17 – OUTPUT CELL (OUT_CELL) ...................................................276
FIGURE 18 – BI-DIRECTIONAL CELL (IO_CELL) .........................................276
FIGURE 19 – LAYOUT OF OUTPUT ENABLE AND BI-DIRECTIONAL CELLS
..............................................................................................................277
FIGURE 20 – BOUNDARY SCAN ARCHITECTURE ......................................279
FIGURE 21 – TAP CONTROLLER FINITE STATE MACHINE ........................281
FIGURE 22 – UNCHANNELISED RECEIVE LINK TIMING ............................285
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE x
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet PM7364.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| PM7364 | Frame Engine and Datalink Manager | PMC-Sierra |
| PM7366 | FRAME ENGINE AND DATA LINK MANAGER | PMC-Sierra |
| PM7367 | 32 link / 32 Channel Data Link Manager with PCI Interface | PMC-Sierra |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |