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PM7380 PDF 데이터시트 ( Data , Function )

부품번호 PM7380 기능
기능 FRAME ENGINE AND DATA LINK MANAGER 32P672
제조업체 PMC-Sierra
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PM7380 데이터시트, 핀배열, 회로
RELEASED
DATA SHEET
PMC-1990262
ISSUE 5
PM7380 FREEDM-32P672
FRAME ENGINE AND DATA LINK MANAGER 32P672
PM7380
FREEDM™-32P672
FRAME ENGINE AND DATALINK
MANAGER 32P672
DATA SHEET
PROPRIETARY AND CONFIDENTIAL
ISSUE 5: AUGUST 2001
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE




PM7380 pdf, 반도체, 판매, 대치품
RELEASED
DATA SHEET
PMC-1990262
PM7380 FREEDM-32P672
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 32P672
9.5.2 DMA TRANSACTION CONTROLLER...........................56
9.5.3 WRITE DATA PIPELINE/MUX .......................................56
9.5.4 DESCRIPTOR INFORMATION CACHE ........................56
9.5.5 FREE QUEUE CACHE ..................................................57
9.6 PCI CONTROLLER......................................................................57
9.6.1 MASTER MACHINE ......................................................58
9.6.2 MASTER LOCAL BUS INTERFACE..............................60
9.6.3 TARGET MACHINE .......................................................61
9.6.4 CBI BUS INTERFACE ...................................................63
9.6.5 ERROR / BUS CONTROL .............................................63
9.7 TRANSMIT DMA CONTROLLER.................................................63
9.7.1 DATA STRUCTURES ....................................................64
9.7.2 TASK PRIORITIES ........................................................76
9.7.3 DMA TRANSACTION CONTROLLER...........................76
9.7.4 READ DATA PIPELINE..................................................76
9.7.5 DESCRIPTOR INFORMATION CACHE ........................76
9.7.6 FREE QUEUE CACHE ..................................................77
9.8 TRANSMIT HDLC CONTROLLER / PARTIAL PACKET BUFFER77
9.8.1 TRANSMIT HDLC PROCESSOR..................................77
9.8.2 TRANSMIT PARTIAL PACKET BUFFER PROCESSOR78
9.9 TRANSMIT CHANNEL ASSIGNER .............................................80
9.9.1 LINE INTERFACE TRANSLATOR (LIT) ........................82
9.9.2 LINE INTERFACE..........................................................82
9.9.3 PRIORITY ENCODER ...................................................83
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE iii

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PM7380 전자부품, 판매, 대치품
RELEASED
DATA SHEET
PMC-1990262
ISSUE 5
PM7380 FREEDM-32P672
FRAME ENGINE AND DATA LINK MANAGER 32P672
LIST OF FIGURES
FIGURE 1 – H-MVIP PROTOCOL ....................................................................38
FIGURE 2 – HDLC FRAME...............................................................................39
FIGURE 3 – CRC GENERATOR.......................................................................39
FIGURE 4 – PARTIAL PACKET BUFFER STRUCTURE ..................................45
FIGURE 5 – RECEIVE PACKET DESCRIPTOR...............................................47
FIGURE 6 – RECEIVE PACKET DESCRIPTOR TABLE...................................50
FIGURE 7 – RPDRF AND RPDRR QUEUES ...................................................52
FIGURE 8 – RPDRR QUEUE OPERATION......................................................54
FIGURE 9 – RECEIVE CHANNEL DESCRIPTOR REFERENCE TABLE.........55
FIGURE 10 – GPIC ADDRESS MAP ................................................................62
FIGURE 11 – TRANSMIT DESCRIPTOR..........................................................64
FIGURE 12 – TRANSMIT DESCRIPTOR TABLE .............................................68
FIGURE 13 – TDRR AND TDRF QUEUES .......................................................70
FIGURE 14 – TRANSMIT CHANNEL DESCRIPTOR REFERENCE TABLE ....72
FIGURE 15 – TD LINKING................................................................................75
FIGURE 16 – PARTIAL PACKET BUFFER STRUCTURE ................................79
FIGURE 17 – INPUT OBSERVATION CELL (IN_CELL) .................................279
FIGURE 18 – OUTPUT CELL (OUT_CELL) ...................................................280
FIGURE 19 – BI-DIRECTIONAL CELL (IO_CELL) .........................................280
FIGURE 20 – LAYOUT OF OUTPUT ENABLE AND BI-DIRECTIONAL CELLS
..............................................................................................................281
FIGURE 21 – BOUNDARY SCAN ARCHITECTURE ......................................283
FIGURE 22 – TAP CONTROLLER FINITE STATE MACHINE ........................285
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE vi

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