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PM7389 PDF 데이터시트 ( Data , Function )

부품번호 PM7389 기능
기능 Frame Engine and Datalink Manager
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PM7389 데이터시트, 핀배열, 회로
Preliminary
Frame Engine and Datalink Manager
PM7389
FREEDM 84A1024
FEATURES
• Single-chip multi-channel packet
processor supporting a maximum
aggregate bandwidth of 156 Mbit/s for
line rate throughput transfers of packet
sizes from 40 to 9.6 Kbytes, for up to
an aggregate of 84 T1s, 63 E1s, or 3
DS-3s.
• Provides simultaneous support of
PPP, Frame Relay, Multilink-PPP and
Multilink-Frame Relay protocols.
Alternative protocols supported via
HDLC termination and full packet store
of the data within the HDLC structure.
MULTILINK PPP AND FRAME
RELAY BUNDLES
• Capable of supporting fragment sizes
from 1 to 9.6 Kbytes.
• Support for 3 egress fragmentation
sizes (128, 256, and 512 bytes)
configurable on a per multilink bundle.
Optionally full packet transfers are
supported on a per bundle basis.
• Supports up to 42 multilink bundles
with up to 12 member links per bundle.
These bundles are composed of
independent HDLC channels.
• Support for up to 100ms of intra bundle
skew in the receive direction when
supporting the minimum fragment size.
• Support for PPP header compression
as per RFC 1661.
PPP
• Support for 16 COS levels in
accordance with RFC 2686.
• Either 12 bit or 24 bit sequence
number, with short and long fragment
header formats, is supported.
• Link Control protocol packets are
identified by the PID as control
protocols and will be forwarded to the
Any-PHY interface.
FRAME RELAY
• Link layer address lookup can be
performed based on HDLC channel
and 10 bit DLCI for HDLC channels
supporting Frame Relay protocols.
• The lookup algorithm can support a
maximum of 16 K connection
identifiers (CIs) amongst multilink FR
bundles. The connection identifiers
are ignored in singlelink FR channels.
• Control frames are identified and
forwarded to Any-PHY interface.
• 12 bit sequence numbers supported.
• FECN, BECN, and DE ingress
processing as per FRF.12.
BLOCK DIAGRAM
ACIFP
CIFPOUT
ADATA[7:0]
ADP
APL
AV5
AJUST_REQ
AACTIVE
ADETECT[1:0]
REFCLK
DDATA[7:0]
DDP
DPL
DV5
DC1FP
DDLL-
140
JTAG
Insert
SBI
(INSBI)
Transmit
Channel
Assigner
(TCAS-12)
Tx HDLC
Processor /
Partial Packet
Buffer
(THDL-12)
Performance
Monitor
(PM-12)
Extract
SBI
(EXSBI)
Receive
Channel
Assigner
(RCAS-12)
Rx HDLC
Processor /
Partial Packet
Buffer
(RHDL-12)
Microprocessor I/F (BUMP2)
Egress
Queue
Manager
(EQM-12)
Tx
Fragment
Builder
(TFRAG)
Tx ANY-PHY
I/F (TAPI-12)
SRAM
Controller
(SRAMC)
CB DRAM
Controller
(CB_DRAMC)
Rx
Fragment
Builder
(RFRAG)
Frame
Builder
(FRMBLD)
Ingress
Queue
Manager
(EQM-12)
RS DRAM
Controller
(RS_DRAMC)
Rx ANY-PHY
I/F
(RAPI-12)
Data
Control
TXCLK
TXADDR[15:0]
TPA
TXDATA[15:0]
TXPRTY
TRDY
TSX
TEOP
TMOD
TERR
CCDAT[35:0]
CCADD[17:0]
CCWEB
CCSELB
CCBSELB[1:0]
CBDAT[47:0]
CBADD[12:0]
CBW EB
CBCSB
CBRASB
CBCASB
CBBS[1:0]
RXCLK
RXADDR[3:0]
RPA
RENB
RXDATA[15:0]
RXPRTY
RVAL
RSX
RSOP
REOP
RMOD
RERR
PMC-1991477 (r2)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERSINTERNAL USE
© Copyright PMC-Sierra, Inc. 2001






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