PDF PNX3000HL Data sheet ( Hoja de datos )

Número de pieza	PNX3000HL
Descripción	Analog front end for digital video processors
Fabricantes	Philips
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No Preview Available ! INTEGRATED CIRCUITS DATA SHEET PNX3000 Analog front end for digital video processors Preliminary speciﬁcation Supersedes data of 2004 Jun 24 2004 Oct 04 1 page Philips Semiconductors Analog front end for digital video processors Preliminary speciﬁcation PNX3000 5 BLOCK DIAGRAM handbook, full pagewidth SIFAGC 1× CVBSOUTA CVBSOUTB 2NDSIFEXT (FMRAD) CVBSOUTIF SIFIN 2 VIFIN 2 DTVIFIN 2 DTVIFAGC TUNERAGC DTVIFPLL VIFPLL CVBS0 CVBS1 CVBS2 CVBS/Y3 C3 CVBS/Y4 C4 YCOMB CCOMB CVBS_DTV R1/PR1/V1 G1/Y1/Y1 B1/PB1/U1 R2/PR2/V2 G2/Y2/Y2 B2/PB2/U2 MIC1 2 MIC2 2 SIF AMP QSS MIXER & AM SND DEMOD Fpc 2nd SIF internal DTV 1st IF SWITCH 2 DTVOUT IF 2 SWITCH VIF AMP VIF PLL & DTVIF MIXER SNDTRAP & GROUP DELAY DTV 2nd IF PNX3000 CVBS_IF AM sound CLP_YUV ICLP RGB/YUV MATRIX & SWITCH CVBS PRIM. SWITCH CLP_PRIM CVBS OUT SWITCH & CVBS SEC. SWITCH CLP_SEC L1/AMint AL D CVBS/Y_PRIM C VIDEO IDENT ICLP 2ndSIF AGC DET A 10 D CLK VCA CVBS_SEC Yyuv U V A 10 D ICLP CLK ICLP A 10 D CLK A 10 D R1/AMext AR D 2 primary digital audio secondary digital audio CLK MIC AMPS L2/MIC1/PipMono AL D R2/MIC2/AM AR D 2 MIC1 AM int MIC2 AUDIO SWITCH (DIGITAL OUT) 6.75 MHz AUDIO SWITCH (ANALOG OUT) AUDIO AMPS 297 MHz DATALINK PLL 27 MHz 13.5 MHz 54 MHz ADC CLOCK PLL CLP_PRIM CLP_YUV CLP_SEC DATA 4 LINK 1 DLINK1 297 MHz 2NDSIFAGC DATA 4 LINK 3 DLINK3 297 MHz DATA 4 LINK 2 DLINK2 297 MHz BAND GAP REF BGDEC VDEFLO VDEFLS VAUDO VAUDS RREF VD2V5 VDEFL VAUD DIVIDER TIMING CIRCUIT XREF 13.5 or 27 MHz HV_PRIM HV_SEC VOLTAGE TO CURRENT I2C-BUS INTERFACE IRQ R1 R2 R3 R4 R5 L1 L2 L3 L4 L5 AM EXT DSNDL1 LINEL SCART2R DSNDR1 LINER SCART2L DSNDL2 SCART1L DSNDR2 SCART1R EWVIN REW MCE430 ADR SCL SDA EWIOUT Fig.1 Block diagram. 2004 Oct 04 5 5 Page Philips Semiconductors Analog front end for digital video processors Preliminary speciﬁcation PNX3000 7 FUNCTIONAL DESCRIPTION 7.1 Vision IF The IF amplifier contains 3 AC-coupled control stages which have a total gain control range of more than 66 dB. The video signal is demodulated by means of an alignment-free PLL carrier regenerator with an internal VCO. This VCO is calibrated by means of a digital control circuit which uses the external crystal frequency as a reference. The frequency setting for the various standards (33.4 MHz, 33.9 MHz, 38 MHz, 38.9 MHz, 45.75 MHz and 58.75 MHz) is realised via the I2C-bus. To improve performance for phase modulated carrier signals the control speed of the PLL can be increased by setting bit FFI. The AFC output is generated by the digital control circuit of the IF PLL demodulator and can be read via the I2C-bus. For fast search tuning systems the window of the AFC can be increased with a factor of three with bus bit AFW. The AGC-detector operates on top sync or top white level. The demodulation polarity is switched via the I2C-bus. The AGC detector capacitor is integrated. The time-constant can be chosen via I2C-bus bits AGC1 and AGC0. The AGC has also an external mode which is activated by bit AGCM. In this mode the IF gain is determined by an external voltage on pin DTVIFAGC. The IC has an integrated sound trap filter. The filter is constructed as a cascade of three separate traps, to realize sufficient suppression of the first and second sound carriers. The trap frequencies are selected via the I2C-bus. The IC has an integrated group delay correction filter. The filter can be switched between the PAL BG curve and a flat group delay response characteristic. This has the advantage that in multi-standard receivers the video SAW filter does not need to be switchable. 7.2 DTV IF Apart from processing analog TV signals, the IF circuit can also be used to preprocess digital TV signals before they are sent to a DTV channel decoder. For this application the two modes of operation are DTV 1st IF and DTV 2nd IF. For both operating modes the IF PLL must be set to synthesizer mode. In DTV 1st IF mode only the AGC function of the IF circuit is used, so the DTV channel decoder must be able to handle the 1st IF frequency. Because the AGC detector operates on the down-mixed 2nd IF signal, it is still important to program a valid frequency for the IF VCO. It is recommended to set the frequency of the VCO to a value that is approximately 4 MHz higher than the incoming 1st IF centre frequency. In DTV 2nd IF mode the 2nd IF signal is obtained by down-mixing the incoming DTV IF signal with the IF VCO signal. The low-pass filtered DTV 2nd IF signal is available as a differential signal at the DTV output. This signal may have a maximum bandwidth of 10 MHz. The VCO frequency is programmed via the I2C-bus in steps of 250 kHz. In DTV mode the AGC time constant is determined by a capacitor on pin DTVIFAGC. There are two AGC modes: internal and external. In the internal AGC mode the gain is controlled by an internal AGC detector. The external AGC mode is activated by bit AGCM. In this mode the appropriate AGC pin is used as input, so that the IF gain can be controlled by the DTV channel decoder. The IF PLL has two pins for connection of the PLL loop filters, one for analog TV and one for DTV. This allows each loop filter to be optimized for its application. 7.3 Sound IF The PNX3000 has a separate sound IF input to enable quasi-split sound applications. The sound IF amplifier is similar to the vision IF amplifier and has a gain control range of about 55 dB. The AGC detector measures the average level of the AM or FM SIF carrier and ensures a constant signal amplitude for the AM demodulator and Quasi-Split Sound (QSS) mixer. The single reference QSS mixer is realised by a multiplier. In this multiplier the SIF signal is converted to the intercarrier frequency by mixing it with the regenerated picture carrier from the video IF VCO. With this system a high performance stereo sound processing can be achieved. For applications without a SIF SAW filter the IC can also be used in intercarrier mode. In this mode the composite video signal from the VIF amplifier is fed to the QSS mixer and converted to the intercarrier frequency. AM sound demodulation is realised in the analog domain by the QSS mixer. The modulated SIF signal is multiplied in phase with the limited SIF signal. The demodulator output signal is low-pass filtered for suppression of the carrier harmonics. The demodulated AM signal can be digitized by one of the audio ADCs. The QSS mixer can also be used for down-mixing an FM radio IF signal to an intercarrier frequency, so that it can be demodulated by the digital decoder. The IF PLL must be set to synthesizer mode in this case. The preferred solution is to supply the FM radio signal via a 2004 Oct 04 11 11 Page

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